Engineering Elegance

Image Segmentation

Considering the issues with color detection method in the previous section method used for the image processing section of the project, the Image segmentation method was tested out. Considering that the tracking part of the system once the object is identified, the focus was given on understanding, implementing and testing the segmentation method. Some time was also spent to complete a go to goal swarm algorithm that was being developed for a while now. Image segmentation Segmentation is basically separating Read more

By [email protected], ago

Quadcopter Remote Eavesdropping

Almost all of the week was spent trying to read the SPI bus on the Quadcopter remote control to try to understand as well as decipher the communication protocols and the reading addresses for the Quadcopter. There were some useful reading from the Quadcopter remote which are discussed in detail but some possible hardware issue also propped out. Using the Logic Analyzer During the week, a logic analyzer was used to try and eavesdrop on the exact SPI communication between Read more

By [email protected], ago

Fixes and Location Detection

It has been a long time since my last blog post. My progress has been slow over the past 4 months but the important thing is that I’m back in Malaysia and have gotten back to work on the project at hand. Since my last post, a lot of aspects of the project has changed and I’ll be explaining this changes in this post and giving an overview on how the whole process will be from this point on. Program Read more

By [email protected], ago

Certificate Downloads

I always wondered how some Certificate Authorities (CA) got their certificates installed in browsers directly, without the user having to import it manually. It took a bit of extra google-fu. So, I thought it pertinent to note things down here. The key to doing it seems to be to use the appropriate mime type when downloading the certificate file. There are several that are supported by the Mozilla browser: application/x-x509-ca-cert application/x-x509-user-cert applicaiton/x-x509-email-cert As each name implies, it is used to Read more

By Shawn, ago
http://www.sxc.hu/photo/206155

Increasing LTSP Framerate

Given that we are presently using an LTSP setup in our office, we could continue to use our old desktops as terminals while investing in better shared server hardware. While most of the desktop terminals were running fine, capable of full-HD playback, one machine was unable to do so. This machine was an older Compaq desktop model CQ2320D that came with an Atom 330 and a 100Mbps built-in LAN. Initial performance was terrible, with horrible frame-rates even for normal desktop Read more

By Shawn, ago

C++11 Regular Expressions

Part of our project requires the use of regular expressions, which are now a part of the C++11 standard. However, getting things working was not completely straight-forward. All our development machines are running Ubuntu 14.04 LTS and we are using CLANG as our default compiler. Every C++11 regular expression example compiles perfectly using: $ clang++ -std=c++11 regexp.cc However, running the program inadvertently results in it crashing each and every time with the following error. terminate called after throwing an instance Read more

By Shawn, ago

Generic Automated Test Bench

The ultimate future goal is to create a generic Automated Test Bench that can be used with any of our IO cores. Of course the test vectors testing each core has to be different. However, since all our cores use wishbone bus this simplifies creating a generic solution. In this final post, I’ll list down the possible problems with creating a generic test bench and propose a solution for each one of them. 1. The cores I/O pins have different Read more

By [email protected], ago

List of tests for each IO core

I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in a separate file. This post will list down the tests conducted for each device GPIO Write to the control register to set the data direction Write to the data register Read more

By [email protected], ago

IO Cores Automated Test Benches

This post is a documentation of the final version of automated test benches created to verify our IO cores. The test benches have been created for the our GPIO, Master SPI, Slave SPI, UART & I2C master and slave. The test benches verify only the behavior of those devices within their specs. It doesn’t have any random tests or tests for their behavior out of their specs. Here is an overall explanation of how the test benches work First, each Read more

By [email protected], ago

Automated Test Bench Algorithms

In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This is opposing to the normal test benches where a waveform or textual dump of signals is generated and the user has to verify the correctness of the outputs himself. In Read more

By [email protected], ago