Engineering Elegance

Instruction Set Architecture

RISC-V instruction set architecture (ISA) is designed to support computer architecture research and education, and completely free for academia and industry use. By using the reference of RISCV-Angel, which is running with the RV64 (64-bit) architecture. My task is to make sure that the RISCV-Angel is able to run on the RV32 (32-bit) architecture as well. The debugging of the Hello_World program is not going well as I am still getting the “undefined error 0”. Thanks to my supervisor, whom taught me Read more

By [email protected], ago

Schematics Modifications

Now for real, the circuit is finished, and I have started with assigning and creating the footprints for the components. There are no one major updates this week, but rather a lot of changes and modifications to the schematics. As usual, here is the visual diff for this week. Additions are in cyan, and deletions are in red. Now to the details. Adding SPI flash memory Originally, there was only microSD card connected to both the FPGA and the PIC18 Read more

By [email protected], ago

Verilog Integration

This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: To begin with, I’ll first talk about the changes I made on my way of creating the Verilog top level module from the C++ code. If you still remember we Read more

By [email protected], ago

4-Pin ICSP and USB

Good news everyone, the circuit is finished 😀 ! Well, not so fast! Now everything is connected, but there are some last minute modifications to the circuit that were introduced just now. I will work on those first thing next week, and hopefully, I will start with the PCB layout. Here are the updates for the last week. First, here is the visual diff of the root sheet. Edit from last week: Cyan is Additions, and red are Deletions. In-Circuit Read more

By [email protected], ago

JavaScript and Witty

This week is pretty challenging, I was assigned on task of putting a CPU into web application. The first thing to be done is to analyze the code of the CPU, it was written in pure JavaScript. The Best Way to Learn JavaScript I found out that the previous learning on JavaScript is too shallow, the knowledge of JavaScript learning from website is always not sufficient to be applied in project. However, the  best way to learn would be hands-on Read more

By [email protected], ago

Data2mem Verification

Progressing from where I stopped last week, this week I had to finish everything up and make sure that everything works as it’s supposed to. Before I go in details and describe what I have done, I have to clear some stuff that were left from last week up regarding the placement of the BRAM. Location of BRAMs: In my blog entry of last week I have declared that I had some concerns regarding the location of BRAM (Refer to Read more

By [email protected], ago

Minimal Bitstream Size

I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is just a straight-forward 8-bit binary counter. The results are: LX25 Raw/Compressed: 801556/233934 LX16 Raw/Compressed: 464290/134942 LX9 Raw/Compressed: 340697/118773 The sizes stayed the same with and without CRC checking. Looks like the memory storage needed is between 8Mbits (raw) and 1Mbits (compressed).

By Shawn, ago

Hello World

Hello everyone, my name is Ayman and I am doing my Final Year Project under the supervision of Dr. Shawn Tan. In my first blog post I will describe my project, what I have been doing in the past weeks, and what I will do next. The first paragraph is a general description of my FYP, those familiar with the topic can skip it if they want to. My FYP project is based on a project I want to execute Read more

By aymansahal, ago
http://www.zedboard.org/sites/default/files/pictures/ZedBoard_RevA_sideA_0_0.jpg

JSON v XML

There are a whole bunch of JSON v XML posts out there. So, I will not rehash the various arguments on which is better. However, we needed to select a file format to store configuration information. To make things convenient, we decided to use the Boost::Property_Tree library. So, this is essentially about how the Boost library performs when parsing JSON and XML. The sample JSON and XML files were obtained from the JSON examples website. After writing a simple program Read more

By Shawn, ago

Powering the Board and Connecting Ports

I continues working on the schematics this week. By now, almost all the major components in the circuit are connected. Last week I connected the Ethernet jack, SD card, and some of the microcontroller connections. This week I did the connections for the USB port power pins, FPGA I/O ports, the rest of microcontroller connections, and I researched the possibility of sharing the oscillator with two ICs. If you are interesting in reading more about the problems and the configuration Read more

By [email protected], ago