Synthesis of Verilog
This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that describes the circuit I drew. Initially, I started to rely on Icarus Verilog Simulator, which turns out that the output waveform is the ideal waveform that I was looking for. After working and tested for several timing signals, I decided to test it on the Xilinx ISE tools to check on my work. Read more

