For this week, I work on instantiating the modules. Each signals’ name need to be the same as object’s name. For example, a signal named ‘ack_i’ should have an output like ‘B1_ack_i’ as ‘B1’ is the object name. This is achieved by using substring in an AUTO_TEMPLATE. Then I make sure the necessary information will be successfully captured by the computer. For now, I have each module instantiated and ready to be connected to the computer. To allow communication between Read more
I basically did the text processing part on the first day of this week. By using regex, the program is able to read through a template and output the signals’ name on a Verilog file. But this technique is not suitable as the user has to make sure that the device is compatible with the template. I basically spent most of the time studying JointJS before I get to talk to Dr. Shawn. We realized the problem of reading the Read more
This week I have started doing my first task which is I have to deal with SQL. At first I have to struggle a little bit to understand how SQL works in CakePHP. Luckily Dr Shawn gave me some tips and advices. He said I can work with SQL inside the controller, table or manually which is the last option. For this project, it was previously done inside controller so for me to understand how to make SQL works he Read more
Modifying the debouncer design was how this week started and end for me. I used a counter for my previous design but this was not recommended by Dr. Shawn since it takes up a lot of space and the design could be simplified even further just by using a Linear Feedback Shift Register (LFSR). LFSR use a shift register for the input bits that is dependent on its previous state. In a way, the design would be more efficient and Read more
After delaying the comparative algorithm aspects of the application for some time, it was great being able to finally make some implementable progress on it this week. It began with the primitive idea of using the normal distribution to estimate relative difference in scoring between two players based on the percentage of judges in favour of a player over the other. This did pose a minor problem in the event that all judges vote in favour of or against a Read more
I started off this week by troubleshooting and testing the flash functions. In harmony there are two non-volatile memory drivers, NVM and Flash. Usage of the flash driver is simpler compared to NVM. The functions allow you to write a word, quad word, or a defined row size. Though you must handle bit-shifting when writing large data. You’ll find how the functions work in this documentation. After I’ve verified its functionality I attempted to test it by writing a dummy key for the Read more
Bouncing is the likelihood of metals to come into contact with each other, when the contact is opened or closed, producing unwanted multiple signals. Debouncing is the method of making sure only one desired signal is produced based on a single opening or closing of a contact. I have proceeded with the next module, push button. Dr. Shawn said that it required a debouncer since the push button has the tendency to bounce. I find it interesting learning how debouncing Read more
This week was mainly spent finishing up the flow of the program. I first started with modifying the data file importer to accommodate the requested changes and continued with the addition of the CRUD functionalities of the admin page. I then started work on the MC page to handle the entire event. This mainly involved handling the logic on the flow of the program and how the various roles interact with each other. Then followed some automation of the process Read more
For this week my progress is still slow. I continued my study about CakePHP and at the same time I tried my best to understand the structure of the first project that Dr.Shawn gave me. I also do some study about PHP just to recall back what I have learned in university. On the last day of the week, I met Dr.Shawn and he gave tasks to me which I need to fix two bugs in the website. He explained Read more
I work on generating Verilog version of source code based on user input which is coded in C++ this week. I study Verilog-mode and the way of this tool functions to properly instantiate the signals’ name. I make sure the program labels each device respectively to user’s input while doing the translation from C++ to Verilog in order to organize the system and it also helps when I need to come out with a naming convention for the connection between Read more