Input Characteristics Determine Debounce Time
After much reading and some calculations, I learnt that theoretically the ideal bits of the LFSR counter in my design should result in the range of 300 µs to 5 ms debounce time. The width had to be quite large since the FPGA board clock speed was 100 MHz. For validation of the specific time to be put in the design, I tested the push button with a range of LFSR widths. I started with low widths that gives about Read more