This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining Keyes modules with minor adjustments for each. While I understood that the analog value is obtained by measuring the time for the capacitor to discharge, as different resistance values would result in a different slew rate, I have been trying all week to get an time Read more
This blog post marks the end of my first week in Aeste. In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I am able to understand the work on Alya’s project as she has concluded her internship. I spent a couple of days just getting myself familiar with Verilog code, reading examples and how it’s implemented as well as redrawing the logic circuits that correspond to Verilog code. Moreover, I have learnt to use Read more
This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Instruction memory is equivalent to ROM and data memory is RAM. For the company’s current choice of fpga (Xilinx Spartan6 LX9), each block of RAM is 18kbit configurable up to Read more
Basically this week was quiet good for me. After such a long time stuck and trying to fix the bug at last I managed to fix it. The main problem is the way the code filter the fields were wrong which eventually made the aliases and propertyName that I used in View file are not working. After finish fixing the filter, I proceed to fix all the pages that related to it. This bug made me realize that I need Read more
I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on the project by going through one by one from the basics to the complicated process of designing in Verilog. At first, I started with showing the Verilog mode in Emacs and viewing waveforms in GTKwave after writing a test bench. After that, I demonstrated the use Read more
I made a mistake when I was integrating the simulator’s functionalities into the other project. I got the wrong idea for testing the simulator but luckily Dr. Shawn corrected me and he taught me where to start with. After I have added some files and separated the back-end and front-end, I decided to commit the changes and push it to the develop branch. When I check the logs before I push the changes, I realized that the latest commits were Read more
This week I managed to finish off the REST API except for the REST client specific specifications which at that time was still undecided. Hence, I proceeded with adding the SMTP functionalities. It took me a while to decide on the best way to take into account the possibility of an email not being successfully sent to its recipient until Dr. Shawn told me that it was somewhat unreliable to predict success anyway so that was a bit of effort Read more
I generally receive a stunned look when I tell people that we build everything with C++ where possible, including web applications. It happened again recently and they will usually ask me – Why?!!! I’d like to document some reasons why we chose to use C++ to build web applications here. I shall preface by saying that we will use whatever language that the client specifies for client projects. However, for our own internal projects we prefer C++ over everything else. Read more
This week, I finished connecting each module to CPU via a customizable switch. I learned the importance of flexibility in design while I was designing the naming convention for different modules and their signal’s name. Other than creating a working design, I make sure the design is elegant and simple. Also, I recorded the technique I used in Wiki on Github to ensure the next intern will understand it clearly. Next, I will be working on generating a UCF file. Read more
This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made a program to extract information from generated Verilog file, so that the naming of pins from Json side matches with the naming on Verilog side. But this causes the program to be unstable as the timing of generating file could be simultaneous. Therefore, I redesign the Read more