Diving right into Synthesis
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer level (RTL), logical gate and physical gate level description. Its main purpose, however, was to perform behavioral and RTL synthesis. In addition, there were several FPGAs which could be synthesized Read more