I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals below based on the Wishbone specification. DAT_I: It denoted the data input array, the size of the array was determined by the port size DAT_O: It denoted the data input Read more
This is week five of my internship at Aeste Works. To move forward to what I have to do to implement USB CDC ECM class for ethernet over usb, I’d have to first migrate the USB CDC ACM demo from the PIC32MX which I had been working on last week to the PIC32MZ in which the company’s own board utilises. I was provided a schematic showing the pinouts of the custom board and was tasked to implement a simple LED Read more
I’ve finally implemented the base functionalities of the project, and tested that everything works as expected. The only thing that I have left hanging in the dark is finding out how to get the automatic installation of client certificates into browser working. Nevertheless, the application is almost ready to be deployed soon, even if we have to resort to having the users do manual installation of their certificate in the worst case scenario, once further testing and final checks have Read more
This is my fourth week as an Intern at Aeste Works. My main target this week was to configure the PIC32MX microcontroller as a Universal Serial Bus Communications Class Device that utilizes the Ethernet Networking Control Model (ECM) in allowing the exchange of Ethernet-framed data between device and host. The first two days of the week were going through Microchip’s USB library documentation and USB Specification for Communication Devices to understand how the USB stack is structured specifically for the PIC32MX. Read more
Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important information was stored in a map. Std::map was an associative container to store elements, i.e. key-value pairs. A simple example would be std::map<int, int> map, where the map stored key-value Read more
This week is the week where I try to finish up all of the basic functionalities of the application. What I had left was to figure out how to create a custom x509v3 extension with Botan C++. As recommended by Dr Shawn, I used the UserRole extension, as shown here. Creating the UserRole extension with Botan C++ involves having a self-defined class to inherit the properties of Botan’s Certificate_Extension class. Since it is an abstract class, there are some methods Read more
This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan 6 FPGA configured by a PIC32 microcontroller and thus the objective of studying the documentation of the other two were to determine whether or not a different configuration protocol will Read more
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer level (RTL), logical gate and physical gate level description. Its main purpose, however, was to perform behavioral and RTL synthesis. In addition, there were several FPGAs which could be synthesized Read more
The major thing that I managed to get done by this week was the implementation of interfacing with the WooCommerce REST API. As a reminder, this is only done by the application when a new subscription for an organization certificate is made, and the customer also chooses the option to entrust the management of their certificate to us, hence their intermediate CA certificate will be stored on our server side. This intermediate CA is responsible for issuing client certificates that Read more
This was the second week being an Intern at Aeste. At the start of the week, Dr Shawn explained the overview of the main project that I would be handling during this internship. One of the tasks were to eventually interface a few other popular FPGA’s with the PIC microcontroller on the board aside from the already interfaced Xilinx Spartan FPGA. This would require investigation and research on the required information such as bitstream format as well as programming protocols. Read more