Chronicles from our peeps.
This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining Keyes modules with minor adjustments for each. While I understood that the analog value is obtained Read more
This blog post marks the end of my first week in Aeste. In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I am able to understand the work on Alya’s project as she has concluded her internship. I spent a couple of days just Read more
This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Read more
I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on the project by going through one by one from the basics to the complicated process of Read more
I made a mistake when I was integrating the simulator’s functionalities into the other project. I got the wrong idea for testing the simulator but luckily Dr. Shawn corrected me and he taught me where to start with. After I have added some files and separated the back-end and front-end, Read more
This week I managed to finish off the REST API except for the REST client specific specifications which at that time was still undecided. Hence, I proceeded with adding the SMTP functionalities. It took me a while to decide on the best way to take into account the possibility of Read more
I generally receive a stunned look when I tell people that we build everything with C++ where possible, including web applications. It happened again recently and they will usually ask me – Why?!!! I’d like to document some reasons why we chose to use C++ to build web applications here. Read more
This week, I finished connecting each module to CPU via a customizable switch. I learned the importance of flexibility in design while I was designing the naming convention for different modules and their signal’s name. Other than creating a working design, I make sure the design is elegant and simple. Read more
This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made a program to extract information from generated Verilog file, so that the naming of pins from Read more