Miracle! The design we’ve been working on in the previous week works perfectly! Honestly speaking the main merit goes to my colleagues, as their part was more crucial (mine was just a wishbone master sending some 8-bit combinations through switches), but still, I feel relieved. Funny, I’m pretty sure I Read more…
This lab was really annoying in terms of things that didn’t want to work When trying to export hardware for SDK in PlanAhead error shows [Common 17-49] Internal Data Exception: xps application failed SDK requires gmake, we can solve it by simple linking: cd /usr/bin sudo ln -s make gmake Read more…
As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I Read more…
After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal Read more…
Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange Read more…