Tag: fpga Page 2 of 3

TCPIP Stack Bug

This week I continue trying to figure out how to ‘download’ a huge file with TCP protocol. Set up a USB cdc com port to ease debugging. Fixing…

Configure FPGA with slave serial method

This week I try to fix ‘init_b’ low and get the configuration of spartan 6 working. ‘init_b’ turn high Finally manage to read a HIGH output from ‘init_b’…

Init_B Forever Low

This week I try to configure the FPGA using PIC32 with slave serial method. C array bit file First I convert the binary file of FPGA into C…

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to…

FPGA and PIC comms

This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it. Add a SPI module As…

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the…

PIC32 Serial Console and Configuring a FPGA

This is my tenth week in AESTE. Continue fixing some minor bug for my wolfssl TCP server state machine and adding some additional features. ╭∩╮(︶︿︶)╭∩╮ Correcting some misconception…

WEEK 4: Spartan 6 FPGA

My task of this week is the configuration of FPGA. I had to configure the Spartan 6 XC6SLX9 FPGA in the slave serial mode, by using the USART…

Minimal Bitstream Size

I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is…

Creating the Verilog Top Module

This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror…

Creating User Constraints

After the previous week has finished, this week we were back working on our first project. My task was to generate a UCF that will contain the wiring…

Engineering Design

The task of this week was completely different. We were asked to do some engineering design work .The client company wants to build a device that has the…

Embedded System Design

Doing an internship at a small company is significantly different that doing it at a multinational firm! This is my seventh week here at AESTE and I can…

The big picture and saving time

The project becomes closer to completion with the top level creator being as done as possible. In this post I’ll start by explaining the top level creator and…

Bit streams, Synthesizer and Data2mem

My journey with C++ continues with three engines up and running. The bitgenerator, the software encoding bitstreams to suit our system. The software loader which runs data2mem to…