Tag: fpga Page 2 of 3

Proceeding to SD card

After successfully integrating the FPGA code with ethernet and USB serial, I proceeded to create a test firmware to establish and verify a connection with a micro SD…

Successful integration of FPGA project

The FPGA project has been succesfully integrated into the current project containing the usbcdc and ethernet. Now the test firmware has working ethernet, usb serial port, and also…

Integrating the Projects

This week I started by trying to modify the FPGA code so that it would transfer in chunks of data rather than all in one go. Turns out…

FPGA now working

The FPGA is now configurable using the pic32mz. The cause of the problem was identified as being the clock to the FPGA not being set, and also the ucf…

TCPIP Stack Bug

This week I continue trying to figure out how to ‘download’ a huge file with TCP protocol. Set up a USB cdc com port to ease debugging. Fixing…

Configure FPGA with slave serial method

This week I try to fix ‘init_b’ low and get the configuration of spartan 6 working. ‘init_b’ turn high Finally manage to read a HIGH output from ‘init_b’…

Init_B Forever Low

This week I try to configure the FPGA using PIC32 with slave serial method. C array bit file First I convert the binary file of FPGA into C…

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to…

FPGA and PIC comms

This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it. Add a SPI module As…

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the…

PIC32 Serial Console and Configuring a FPGA

This is my tenth week in AESTE. Continue fixing some minor bug for my wolfssl TCP server state machine and adding some additional features. ╭∩╮(︶︿︶)╭∩╮ Correcting some misconception…

WEEK 4: Spartan 6 FPGA

My task of this week is the configuration of FPGA. I had to configure the Spartan 6 XC6SLX9 FPGA in the slave serial mode, by using the USART…

Minimal Bitstream Size

I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is…

Creating the Verilog Top Module

This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror…

Creating User Constraints

After the previous week has finished, this week we were back working on our first project. My task was to generate a UCF that will contain the wiring…