This week I try to fix ‘init_b’ low and get the configuration of spartan 6 working. ‘init_b’ turn high Finally manage to read a HIGH output from ‘init_b’ of FPGA. The solution was to have PIC32 enabled ‘pull_up’ on the input pin and some additional pic32 initialization set up. Next Read more…
This week I try to configure the FPGA using PIC32 with slave serial method. C array bit file First I convert the binary file of FPGA into C array (Hex format) so that I could use SPI 8bit or 16bit to send the hex data bits by bits into FPGA. Read more…
The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, Read more…
This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it. Add a SPI module As I mentioned on my previous post, my task is to assign the SPI module into the FPGA, to form the communication bridge Read more…
This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the software implementation of demosaicing for various demosaic algorithm, and tested them in Darktable software. The darktable software is very convenient because it Read more…
This is my tenth week in AESTE. Continue fixing some minor bug for my wolfssl TCP server state machine and adding some additional features. ╭∩╮（︶︿︶）╭∩╮ Correcting some misconception For my previous post, I mention about the IP address being different from the one preset in Harmony Configurator, and the solution Read more…
My task of this week is the configuration of FPGA. I had to configure the Spartan 6 XC6SLX9 FPGA in the slave serial mode, by using the USART port in the PIC18F97J60. This is something really new to me and web references are scare. Therefore, the only way is to Read more…
I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is just a straight-forward 8-bit binary counter. The results are: LX25 Raw/Compressed: 801556/233934 LX16 Raw/Compressed: 464290/134942 LX9 Raw/Compressed: 340697/118773 The sizes stayed the Read more…
This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror with witty to extracting the user objects IDs (Check out my previous blog entries for more information ). This week the task Read more…
After the previous week has finished, this week we were back working on our first project. My task was to generate a UCF that will contain the wiring information. At the beginning of week, I had no idea what a UCF file is, nor how to generate it. Also, since Read more…