Hi again !

As the goal for ash1 is to make it as small and as fast as possible. I’ve tried to investigate the size and speed features of ash1.

As we have seen from the previous post, ash1 is pretty small (~500 FPGA slices)… I guess this is super cool if we compare it with a typical MAC Ethernet IP core (~2800 FPGA slices). Moreover, it’s smaller than AEMB processor core (~1500 slices). So in terms of size, the objective is met. However, I had to take into consideration the fact that during compilation, the instruction memory was included in the synthesis process.. and this – as I have temporarily implemented- is variable in size. It depends on what sort of programming I am running on ash1. For instance, having a code snippet of 35 14-bit instructions eats up ~0.5 Kb whereas 3 instructions takes up ~0.041 Kb. So, we should take into account this factor upon assessing ash1 at the end.

Regarding timing constraints, I managed to get ash1 working on at least 50 MHz.. this is pretty acceptable especially if we know that some I/O operations has slow data rates. For instance,   a 10BaseT MII interface, the data is transferred in 4-bit nibbles at 2.5 MHz. Another example is USB low speed data rate , 1.5 Mbps.

Nevertheless, I tried to look up the timing constraint for ash1 using Quartus II- taking into consideration the variable instruction memory size that’s re-setted upon an asynchrnous reset button- . the maximum clock frequency, I could achieve, was 277.3 MHz and this is just awesome !

However, in order to make an accurate estimation of ash1 size and speed, we could exclude the instruction memory unit and perform the analysis !

That’s it for this post ! stay tuned for the next post …