I have finally begun making changes to the K3rangka code, trying to isolate the implementations of running yosys, nextpnr, and other tools into separate classes. Previously, the implementation was within the resource file that handles the HTTP requests. The implementation handled different type of FPGAs through if statements, which was Read more…
My search for the tools in Vivado and Quartus has come to an end. After three days of unsuccessful attempts to track down the processes while running Vivado and find the tools for each part of the design flow, I have given up and decided to resort to tcl commands Read more…
This week, I was focused on finding tools for FPGA boards besides the Ice40 (Lattice ECP5, Xilinx Series 7, and Intel Cyclone V). My starting point was my supervisor’s suggestion to look at project Trellis, X-Ray, and Mistral for each of the boards respectively. Out of the three projects, project Read more…
During my second week of internship, I encountered two unexpected surprises concerned with the project I was given. My project was the continuation of what another intern, Jun Wen, was working on. It was the development of a web application that would simplify the programming of different models of FPGAs. Read more…
This will be my last week of internship in Aeste. I finished up my work on code refactoring. As this will be the last blog entry from me, I would like to write on the learnings and reflections throughout this internship. I have obtained various technical skills, namely Git version Read more…
I mainly focused on generating a multipart message this week. I was using curl to send a multipart formpost previously. For example, curl -kv -F ‘lang=vlog’ -F ‘[email protected]’ http://127.0.0.4:8080/api/v19/workspace.elaborate was used to transfer data to a server. The request body was shown below. (Note: A boundary was a string of Read more…