This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan 6 FPGA configured by a PIC32 microcontroller and thus the objective of studying the documentation of the other two were to determine whether or not a different configuration protocol will be needed to be implemented by the PIC32 to configure the other two FPGA’s. From the documentations, all three FPGA’s can utilise serial configuration that enables an external host, in this case the PIC32 to configure it by a clock and a data pin. Although, the protocol is the same, there are some differences such as data sent to the FPGA on the rising edge or falling edge of the clock, and the different pins that need to be pulled high or low during configuration. As for the bitstream order when the PIC32 configures the FPGA, both Xilinx Spartan & Altera Cyclone are little endian meaning that the least significant bit is stored first while the iCE FPGA is big endian meaning that the most significant bit is stored first. Also, one other information was researched on whether data such as company name and software info can be included in the configuration bitstream. This is possible for Xilinx Spartan and Lattice iCE40 FPGA, however documentation does not explicitly say for Altera Cyclone.
The second task was to familiarise with the CORS protocol from the company’s source code. Cross Origin Resource Sharing (CORS) is a mechanism that allows restricted resources on a webpage to be requested from another domain outside the domain from which the first resource was served. Referring to the Git Wiki and the source code, I was able to understand the different core operations and sequences. The preflight command OPTIONS request will enter the programming mode and process any subsequent request as a programming operation such as DELETE which erases the firmware on the FPGA, PUT which transmits the firmware to the FPGA, and HEAD which validates the firmware.
The last task was to research and understand the protocols on how ethernet can be provided over USB and the difficulty of implementation on the PIC32. There are several protocols for Ethernet-style networking over USB such as RNDIS, a Microsoft vendor protocol, Ethernet Control Model (ECM), Ethernet Emulation Model (EEM), and Network Control Model (NCM) of which the last three are part of the Communications Device Class group of protocol. As far as Microchip USB CDC is concerned, there has been no implementation of these protocols thus far, however looking through the Microchip CDC datasheet, they have support for the Abstract Control Model. Both the ACM and ECM are actually subclasses of the Communications Interface Class and knowing this, they both are similar in terms of data interfaces, communication interfaces and some of the descriptors as well. I’ll have to work ground up from the basics of the ACM class to configure it to work as an ECM to provide ethernet functionality over USB. This’ll be my main task for the coming weeks and I hope I can manage it.