This is my ninth week in AESTE. I spent almost my whole week to study the theory of bootlaoder and how the dual memory work for PIC32MZ. Only the PIC32MZ has dual memory bank, other PIC32 only has one.
Bootloader is used to upgrade the firmware of microcontroller without using any external programmer or debugger such as PICkit 3. Harmony provides two ways to implement this, one is basic method (all PIC32 can use this) and another is live update method (only PIC32MZ can). The difference between these two methods are the live update allow the new firmware store to different memory bank and it can still receive external signal while updating the new firmware. Therefore, for our project we will implement the live update to our PIC32.
How the Live Update work?
For the PIC32MZ, it has dual Boot Flash (BFM Bank 1 and BFM Bank 2) and dual Program Flash memory (PFM Bank 1 and PFM Bank 2). Every time the PIC32 startup, it will check the value of BFxSEQ3 value is valid or not. If the value of CSEQ is complement to TSEQ, this means the BFxSEQ3 value is valid. For example TSEQ value is 0x0004, then the CSEQ will be 0xFFFB (BFxSEQ3 will be 0xFFFB0004). Next, it will check the value of BF1SEQ3 and BF2SEQ3 and compare it. If the BF1SEQ3 is larger than BF2SEQ3, BF1SEQ3 will mapped to lower region. If BF1SEQ3 is equal to BF2SEQ3, BF1SEQ3 will mapped to lower region as well. If the result is BF2SEQ3 larger than BF1SEQ3, BF2SEQ3 will mapped to lower region. If Boot Flash 2 is mapped to lower region, the NVMCON bit 7 (SWAP) has to set as ‘1’.
NVMCON bit 7 = ‘1’ : Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to the upper mapped region.
NVMCON bit 7 =’0′ : Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to the upper mapped region.
Please noted that the NVMCON bit 7 only writable when the WREN =0, the unlock sequence has been performed and disable the global interrupt.
PLIB_INT_Disable(INT_ID_0);
NVMCONbits.WREN=0;
NVMKEY=0XAA996655;
NVMKEY=0X556699AA;
Next, every time PIC32 downloaded the new firmware , we have to update the TSEQ (example: increment by 1). The reason for increment of TSEQ by 1 is because the CSEQ will decrease by 1 in the same time (CSEQ is complement to TSEQ). Therefore, next time the PIC32 will run the new program. This is because PIC32 startup will be mapped Boot Flash Bank 2 to lower region (new firmware) and the Boot Flash bank 1 (old firmware) will mapped to upper region.
Conclusion:
This week I had spent my time to read many forums and datasheet to understand how the live update bootloader works. Next week I hope I can start to test live update in my PIC32MZ.
**note: the comparison between Boot Flash 1 sequence and Boot Flash 2 sequence it should be BFxSEQ3, not BFxSEQ0. The document in Section 52. Flash Memory with Support for Live Update is wrong information. Microchip had update it to BFxSEQ3 in PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family .
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