I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on the project by going through one by one from the basics to the complicated process of designing in Verilog. At first, I started with showing the Verilog mode in Emacs and viewing waveforms in GTKwave after writing a test bench. After that, I demonstrated the use of Xilinx ISE to synthesis and analyse the design made apart from generating the bit file to be loaded to the FPGA board.
I continued to show a method of using USB over IP to connect the FPGA board to the server and ways to load the bit file using iMPACT. I could see that he was catching up fast since he can do it on his own right after the first demonstration. Therefore, I just gave more materials and links to go through on designing in Verilog using Wishbone protocol.
I was glad I could finish all the documentation for every modules that I was able to design. Dr. Shawn said that in the last week of internship, the documentation must be completed so that it can be a good reference for people that are taking over the project. I managed to finish 27 modules out of 36. Although I could not finish all of them in my 6 months of internship, it was satisfying enough considering how slow my progress was at the beginning.
I learnt a lot new things during my internship here and gained valuable knowledge as well as the skills required in designing chips. Furthermore, I got to meet great, intelligent friends and had the privilege of learning chip design from Dr. Shawn himself. This internship surely gave me an experience that I would not have gotten elsewhere.
Farewell! It was a pleasure knowing everyone =)
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