Clocking FPGA and LAN8720 with PIC32MZ
This is my fifteen week in AESTE finishing up my PCB design project. ..-“””””-.. .’ ___ ‘. / .”\ `\ \ ; /, ( | ; ; /_ ‘._ / ; | |- ‘._`) | ; ‘-;-‘ \ ; ; “””” / MY \\ ; \ ‘2 Cents’ / ‘._A Read more…
The Final Week in AESTE
This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM to delay the signal, when it is extremely large cycle to be delayed with. My supervisor Read more…