This week and the coming one will all be about finalizing, testing and documenting everything. This needs to be done for all t3pi I/O devices. In addition, there is a few bugs in c3rdas accelerators that need to be solved. Currently I’m writing my technical report about my internship. I will be posting any relevant diagrams or information from my report. I hope this helps whoever is gonna use my devices later on.
Picking up from last week, it has become crucial to run the synthesis tool at optimization effort level 1 to meet the required timing constraint. Our timing goal is to be able to run the design at 100 MHZ, the intended frequency for t3ras SOC. However, post synthesis timing results with the synthesis tool set to optimization effort level 0 shows a maximum frequency of 94 MHZ. Using optimization effort level 1 results in a 117 MHZ maximum frequency. Thus it’s necessary to run the synthesis tool at effort level 1
I ran across a bug in the GPIO. Originally I have created the Tri-State buffer for the whole bus using a single assignment statement in an always block like this:
gpio_io <= (tris)? port : {(GPIO){1’bz}};
However, this statement is not suitable for creating a bus of Tri-State buffers. The correct way would be to use a for loop. like this:
for (i; i<GPIO; i++) gpio_io[i] <= (tris[i])? port : 1’bz;
Finally, I’ll conclude this post with a gift of functional block diagrams for GPIO, SPI Master and SPI Slave.
GPIO
SPI Master
SPI Slave
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