Basically I was supposed to add a small part to the simulation test bench of AEMB processor so that it’ll print out whenever there is a read or write to an I/O device displaying the address and used value. My mistake is that I didn’t realize I was supposed to edit the Verilog test bench I thought I should edit the C test program and I was all over the place trying to figure out how to do that! My supervisor is probably slamming his keyboard while reading this!!
So in this post I’ll give guidelines how AEMB processor test bench works. I’ll start from the bottom up explaining even the make files included. I intend this post to be helpful to those using AEMB.
You can go through the code of AEMB to understand it’s architecture cause I won’t be able to help you with that part! Now let’s say you wanna test this processor. First of all you gotta write a program to run on it or you can use the demo program provided. In order to write code for AEMB you can use normal C code but you need to include the AEMB core header files.
The provided demo program for AEMB runs several mathematical calculations and does simulations to test memory and interrupts. You just need to run the Make File in SW folder.
You can read about Make files here. Below is what happens inside this make file:
When you use the command Make the Make File runs the first task in it which in this file is testbench. In this task the first action is to compile the testbench.cc for aemb. Here is an explanation of the command used to compile the file.
$(CC) : The compiler used in compilation is the GNU compiler for C++ but a version specific for Micro Blaze microprocessors hence the “mb” at the beginning. More about the Micro Blaze software from here.
$(CFLAGS) : All of the Compiler flags are specific to the Micro Blaze enabling special features and using special devices when compiling. You can learn more about them here
-specs=aemb.specs : Here the compiler is configured to produce code for AEMB. Finally the output of this step is an elf file. More about elf files can be found here or here and this gives some information about Micro Blaze Elf files. A very useful command to analyze ELF files is the readelf command and also objdump.
Next task is the “sim” task which first dumps the content of the elf file for verification purposes and then uses objcopy to create an srec file which is used by the srec-cat program to create a vmem file. This file contains the memory content that’s gonna be loaded into the memory connected to the processor.
Now that you have your program ready in the Vmem file you should run the simulation. The Make File for the simulation can be found in the “sim” folder and here is it’s explanation:
The make file doesn’t compile the Verilog code immediately but it first creates a temporary folder using the mktemp command and then it first produces a list of the names of modules included then uses the uniq command to filter out repeated lines and the sed to remove unwanted lines leaving the file at .fs with only the names of the verilog files needed for compilation. Still it doesn’t compile the files it just uses iverilog to put all the code in one big Verilog file ready for compilation in the next step.
Next step is to compile the verilog code and place the output in a .vvp file then run this file by the vvp simulator and fill it’s memories with the code from the .vmem file.
Finally here is my progress so far: At the moment I know how to write C programs for AEMB, compile it and test it with simulation. I can use the Data2mem to produce memory files and I have my simple AEMB SOC with GPIO inferring everything correctly. All that’s left is to bring all these things together and get some blinking LEDs.