As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I Read more…
After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal Read more…
In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. Read more…