LLVM: Cleaning up instructions
My recent task is to clean up the instructions from LLVM code. One must wonder why do I need to clean up the instructions, well perhaps the definition of my recent task was not adequately explain here.
AEMB is considered as binary compatible to the Xilink Microblaze (Wikipedia link), however it is not a ‘drop in’ replacement. For a quite distinctive example, AEMB does not support floating point instructions. Yet. Fortunately, due to the compatibility of their instruction-set, I was able to start building my custom compiler for AEMB from the existing LLVM Microblaze backend.
But, as mentioned earlier, they are a lot tweaking needs to be done with the existing LLVM code. Hence, come the task to clean up the existing instructions that support floating points. I thought it was quite easy task, well, its not. The problem I was facing right at this moment is that I was unable to get rid anything related to floating points supports without damaging a lot of backend files. All of them are seems to be related to one another, more or less.
Use tablegen command as below to pull up current list of instruction-set of Microblaze LLVM backend.
tblgen -I=/llvm/include/ MBlaze.td -print-enums -class=Instruction
and the list will show up in the terminal.
ADD, ADDC, ADDI, ADDIC, ADDIK, ADDIK32, ADDIKC, ADDK, ADDKC, ADJCALLSTACKDOWN, ADJCALLSTACKUP, AGET, AGETD, AND, ANDI, ANDN, ANDNI, APUT, APUTD, BEQ, BEQD, BEQI, BEQID, BGE, BGED, BGEI, BGEID, BGT, BGTD, BGTI, BGTID, BLE, BLED, BLEI, BLEID, BLT, BLTD, BLTI, BLTID, BNE, BNED, BNEI, BNEID, BR, BRA, BRAD, BRAI, BRAID, BRALD, BRALID, BRD, BRI, BRID, BRK, BRKI, BRLD, BRLID, BRLID32, BSLL, BSLLI, BSRA, BSRAI, BSRL, BSRLI, CAGET, CAGETD, CAPUT, CAPUTD, CAS32, CGET, CGETD, CMP, CMPU, COPY, COPY_TO_REGCLASS, CPUT, CPUTD, DBG_VALUE, EAGET, EAGETD, ECAGET, ECAGETD, ECGET, ECGETD, EGET, EGETD, EH_LABEL, EXTRACT_SUBREG, FADD, FCMP_EQ, FCMP_GE, FCMP_GT, FCMP_LE, FCMP_LT, FCMP_NE, FCMP_UN, FDIV, FINT, FLT, FMUL, FORI, FRSUB, FSQRT, GC_LABEL, GET, GETD, IDIV, IDIVU, IMM, IMPLICIT_DEF, INLINEASM, INSERT_SUBREG, KILL, LAA32, LAD32, LAN32, LAO32, LAS32, LAX32, LBU, LBUI, LBUR, LHU, LHUI, LHUR, LW, LWF, LWFI, LWI, LWR, LWX, MEMBARRIER, MFS, MSRCLR, MSRSET, MTS, MUL, MULH, MULHSU, MULHU, MULI, NAGET, NAGETD, NAPUT, NAPUTD, NCAGET, NCAGETD, NCAPUT, NCAPUTD, NCGET, NCGETD, NCPUT, NCPUTD, NEAGET, NEAGETD, NECAGET, NECAGETD, NECGET, NECGETD, NEGET, NEGETD, NGET, NGETD, NOP, NPUT, NPUTD, OR, ORI, ORI32, PCMPBF, PCMPEQ, PCMPNE, PHI, PROLOG_LABEL, PUT, PUTD, REG_SEQUENCE, RSUB, RSUBC, RSUBI, RSUBIC, RSUBIK, RSUBIKC, RSUBK, RSUBKC, RTBD, RTED, RTID, RTSD, SB, SBI, SBR, SEXT16, SEXT8, SH, SHI, SHR, SRA, SRC, SRL, SUBREG_TO_REG, SW, SWF, SWFI, SWI, SWP32, SWR, SWX, Select_CC, Select_FCC, ShiftL, ShiftRA, ShiftRL, TAGET, TAGETD, TAPUT, TAPUTD, TCAGET, TCAGETD, TCAPUT, TCAPUTD, TCGET, TCGETD, TCPUT, TCPUTD, TEAGET, TEAGETD, TECAGET, TECAGETD, TECGET, TECGETD, TEGET, TEGETD, TGET, TGETD, TNAGET, TNAGETD, TNAPUT, TNAPUTD, TNCAGET, TNCAGETD, TNCAPUT, TNCAPUTD, TNCGET, TNCGETD, TNCPUT, TNCPUTD, TNEAGET, TNEAGETD, TNECAGET, TNECAGETD, TNECGET, TNECGETD, TNEGET, TNEGETD, TNGET, TNGETD, TNPUT, TNPUTD, TPUT, TPUTD, WDC, WDCC, WDCF, WIC, XOR, XORI
As one may notice, there are a lot of instructions that are not supported by AEMB especially instructions involving floating points, division, write to instruction cache and write to data cache.