Great! My blog is in its third decade now. Happily declaring that the project is getting close to the end. This week the final main functionality has been added to it. The project now has the ability to compile the user C++ code, synthesize the top module and finally Read more…
This week and the coming one will all be about finalizing, testing and documenting everything. This needs to be done for all t3pi I/O devices. In addition, there is a few bugs in c3rdas accelerators that need to be solved. Currently I’m writing my technical report about my internship. I Read more…
The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive. First of all the SOC is complete. I have Read more…
Compared to my work the title might be a little too fancy but hopefully our switches will evolve from simple switches to a smart interconnect between the processor and all other system components. Do you remember the second version of the accelerator switch I talked about in my previous blog Read more…
This week we have managed to get an SOC that connects AEMB to SHA1 accelerator and a GPIO. Having only one device at each bus of the AEMB doesn’t require much effort in terms of SOC. The software that we used for testing contained our driver for SHA1. Our demo Read more…
I’ve managed to completely remove the Icache from AEMB. Simulation and FPGA implementation were both a success. However, after the edits AEMB now runs slower because it has to fetch each and every one of it’s instructions through at least two Wishbone cycles. It’s worth mentioning that Before removing the Read more…
Basically I was supposed to add a small part to the simulation test bench of AEMB processor so that it’ll print out whenever there is a read or write to an I/O device displaying the address and used value. My mistake is that I didn’t realize I was supposed to Read more…
My new task is to design the SOC for the current product that we are working on. However, before getting to the actual design there is few tasks that need to be done first. Last week the task was to connect the AEMB2 processor to two block RAMS, one for Read more…