Unfortunately this week has been the least productive for me. In this post, I will summarize my small progress for this week. More importantly, as the blog title suggests, I will post images of AEMB design that I drew during my analysis. I hope this can make up for my slow progress.
(more…)
The journey of analysing AEMB is finally reaching a destination. In this post I will discuss AEMB’s interface with the data memory and with the accelerator bus. Moreover, I will explain the design of the execution unit and highlight some of it’s parts that I can’t comprehend yet. Finally I Read more…
Dissecting AEMB continues. In this post I will give an overview about the instruction set architecture (ISA) of the AEMB and its register file. Finally I’ll explain how AEMB communicates with the data memory and the accelerator bus. Since AEMB code is compiled using the Microblaze toolchain, the ISA of Read more…
Over the past weeks I’ve been exploring the architecture of microprocessors in general and AEMB’s in particular. I wish I can say I am done with dissecting AEMB but I ain’t. In this blog post I will give a quick overview about my project and give a functional description of Read more…
This week and the coming one will all be about finalizing, testing and documenting everything. This needs to be done for all t3pi I/O devices. In addition, there is a few bugs in c3rdas accelerators that need to be solved. Currently I’m writing my technical report about my internship. I Read more…
The project becomes closer to completion with the top level creator being as done as possible. In this post I’ll start by explaining the top level creator and it’s awkward status of being “as done as possible”. Next, I’ll try to make the big picture of our project clearer by Read more…
My journey with C++ continues with three engines up and running. The bitgenerator, the software encoding bitstreams to suit our system. The software loader which runs data2mem to load the elf file into the RAM blocks on the bitstream. Last but nor least the synthesizer which runs Xilinx command line Read more…
After putting my current project on halt for a week time, finally I’m back to track to work on my T3ras project. This week I focus mainly on the execute stage in pipeline to execute and manipulate each of the MicroBlaze instruction sets into semantics operation written in Java. Since Read more…
I’m still working on how to initialize Block RAMs using DATA2MEM software. I have managed to produce a bit file with initialized RAMs. What’s left is to write a linker script to suit our addressing space, write a C file to blink the LEDs using GPIOs and finally get this Read more…
My new task is to design the SOC for the current product that we are working on. However, before getting to the actual design there is few tasks that need to be done first. Last week the task was to connect the AEMB2 processor to two block RAMS, one for Read more…