Engineering Elegance

I2C Revisited

Finalizing I2C continues. Finally the master is fully functioning but tested only through simulation. Here is the Features of the master: Clock Synchronization and Arbitration. Detection of a busy bus. Supports Arbitration loss. Handles Slave induced waits. Capable of repeated start and back to back reads and writes. Future Improvements: Add support for Various I2C speeds Add support for special I2C addresses Solve the drawn back of the master losing arbitration if the required slave is not present The master Read more…

By [email protected], ago

Ahead with the Project

This week was very interesting and yet tiring one! I wrote my networking c++ program and began to understand how machine interacts with each other. That involved too much researching and reading. and most of the time I ended up closed lines. I spent the first few days on researching networks and how to transfer files generated in one machine to another machine which will use it as an input. I wrote my first server and client applications, that moment Read more…

By ademi, ago

PIC18 Interrupt Service Routine

The next thing to do is to initialize the interrupt service routine and also to configure the change on Port B interrupt. By referring to the interrupt that is used by the original demo to calculate the ticks for the blinking LED for the TCP/IP stack, it seems that is necessary to set the global interrupt enable pin, set the interrupt priority enabled pin, low priority interrupt enable pin and high priority interrupt enable pin. The change on Port B Read more…

By chewjiaxien, ago

Its all about SD cards!

Following the disaster of having the 4gb Kingston SD card stop responding, the focus of the week was to find a way to get the non-responsive SD cards to work on the PICTail. A lot of knowledge was gained about the SD cards initialization process (the process at which some of SD cards stop responding). Debugging the MDD Initialization Stack from Microchip Continuing on from the previous week, debugging was continued on the current Initialization process from Microchip. Following the Read more…

By [email protected], ago

Let the Integration Begin

By the end of this month, I should be able to integrate everyone’s project in to mine, and manage them  to produce the desired output I started with Verilog synthesizer.In this process, I’m supposed to execute a shell script that takes a .v file and runs on it three software ,namely xilings , Ngbuilds and Data2mem, to produce a .bit file that contains the configuration bits for the fpga to implement the design of the user. I finish this task Read more…

By ademi, ago

Environment Variables for Xilinx tools

Last week I created a script to run all Xilinx tools required for implementation from the command line. We are using the 14.4 version of Xilinx software. Before using any of the tools in this version a Xilinx script is required to be executed to set required environment variables. However the script sets variables for many Xilinx tools such as Vivado and Plan ahead that are not necessary for our process. Hence, this week I had to dig through Xilinx Read more…

By [email protected], ago

MASTER & SLAVE Modes

My next task was to do something to make the PIC able to switch between the MASTER mode and the SLAVE mode. Generally, the MASTER mode will be the mode where the PIC will be acting as a server and will be receiving the bitstream from the Internet and then save the bitstream into the SD card, while the SLAVE mode will be the mode where the PIC will be reading the bitstream from the SD card and send the Read more…

By chewjiaxien, ago

Redesigning the Base64 Decoder and more about SD cards

This week was a real eye opener in many ways. Physically I was unwell, and mentally I was fatigued. But it throughout the week, I picked up a lot of advice from the supervisor and I hope I was able to implement some of them in my work this week. Bitstream Header File The first task of the week was to look at what was learned from the research done on the Bitstream Header File. As explained previously, the Bitstream Read more…

By [email protected], ago

Interacting with the Compiler

this week was a very frustrating one, full of mysteries and brain teasers… I spent the first few days trying to get the compiler to compile some error code,and get the error message . The challenge was without using shell commands. This lasted for a day or more before I figured it out, but at the end I ended up using shell commands as the code I produce was very risky and may crush the my application. After that , Read more…

By ademi, ago

Prototype SOC completed

The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive. First of all the SOC is complete. I have tested various modular switches differing in the number of devices each accommodates. I have tested switches that can accommodate numbers of devices starting from 2 devices all the way to Read more…

By [email protected], ago