After 16 weeks, 80 days and approximately 640 hours, my time at Aeste Works finally came to an end on 20th December 2013. It feels like such a long time ago that I was fretting about making it on time on my first day. I definitely feel older and wiser about many aspects of engineering, programming and research and design work. This has been the most fruitful four months of work of my life so far. Although I’m sad that Read more
The penultimate week (yes its been 15 weeks already!) at work yielded some fruitful results as the bitstream was able to be read at an optimized speed and some of the older niggling CRC related issues were dealt with. This involved changing the design of how the SD card is used to store the bitstream and in fairness provides a better solution than changing the initialization function to turn the CRC on and off. Fixing the Bitstream reading stack As Read more
Final day, final post, I will explain the things I managed to finalize this week as well as the thing that I couldn’t get to finish. I created a Flippable Master SPI. This master SPI can flip it’s MOSI and MISO pins depending on the value of it’s configuration register. The device has 4 output ports, SCLK, SS, datA and datB. When the configuration register at address zero is NOT SET datA is an input representing MISO and datB is Read more
This week was one where a big setback was experienced in the stack of code for bitstream reading. The stack was then analysed to find the overhead in the code so that the target read times can be achieved. Other than that, some more modifications were made to improve the overall functionality of the program. It was certainly an eventful week. A big Woops! The error in the current code structure was found when the bitstream upload stack was being Read more
The week was spent trying to look for ways to optimize the file upload time to suit the required objective having made some strides on that path during the previous week. Apart from that, a few modifications were made to the MBR editing function. MBR Partition informations It is important to notice that before the SD card is used with the board, it may have already been formatted for use. This means that the SD card may have partitioning informations Read more
Finalizing continues with the SPI. I have previously made a few changes in SPI while integrating it with the system but I hadn’t verified the functionality of SPI after those changes. The most notable change was that one of my if statements was mistakenly inferring a latch. The if statement was missing an else condition. I tested the SPI and it performed as intended on simulation and FPGA. Moreover, I tested the SPI driver. While the FPGA implementation wasn’t very Read more
The week was spent in continuing the ground work done on the Synchronous USART to optimize the Reading process which will subsequently program the FPGA. After solving the problem faced in the week before, time was spent in trying to get the SD card to read the bitstream data as fast as possible. A lot of time was also spent to diagnosing the current writing stack to try and find the bottleneck for it and speeding up the stack as Read more
This week and the coming one will all be about finalizing, testing and documenting everything. This needs to be done for all t3pi I/O devices. In addition, there is a few bugs in c3rdas accelerators that need to be solved. Currently I’m writing my technical report about my internship. I will be posting any relevant diagrams or information from my report. I hope this helps whoever is gonna use my devices later on. Picking up from last week, it has Read more
The project becomes closer to completion with the top level creator being as done as possible. In this post I’ll start by explaining the top level creator and it’s awkward status of being “as done as possible”. Next, I’ll try to make the big picture of our project clearer by explaining the whole process step by step. Most importantly, I’ll showcase my results from analyzing the time consumed by the execution of Xilinx tools using various options. The top level Read more
The optimization of the firmware continued with the focus being on the SD card reading stack. A look into the USART’s synchronous mode functionality was also taken to try and understand how that works. There was also a lot of time spent trying to set up scenarios to break the upload mechanism and see how the system behaves under non-standard conditions. USART synchronous mode The term USART stands for “Universal Synchronous Asynchronous Receiver Transmitter”. So far, only the “Asynchronous” functions Read more