Dissecting AEMB continues. In this post I will give an overview about the instruction set architecture (ISA) of the AEMB and its register file. Finally I’ll explain how AEMB communicates with the data memory and the accelerator bus. Since AEMB code is compiled using the Microblaze toolchain, the ISA of AEMB is pretty much the same ISA for the Microblaze EDK 6.3. Instructions are all 32 bits and they come in two types. Type A have two source registers, A Read more
Over the past weeks I’ve been exploring the architecture of microprocessors in general and AEMB’s in particular. I wish I can say I am done with dissecting AEMB but I ain’t. In this blog post I will give a quick overview about my project and give a functional description of the modules I managed to grasp in AEMB. My project is to create a few versions of the AEMB. The first version is an adjustment to the threading model of Read more
My first week started with tons of reading. I read about the architecture of MicroBlaze. Shawn also told Mostafa and I about the difference between MicroBlaze and AEMB. The most important thing to note is the process of running multiple threads concurrently. I must be able to implement that with the simulator. Nice to meet you Mostafa 🙂 Since the s3laku will be coded from scratch, I also studied various microprocessor simulators’ code. I was able to identify the main Read more
As we are developing a new web application, the question of which framework to use came up. There are many great frameworks around such as cakephp, django, ruby on rails, etc. However, we ended up settling on Witty for one simple reason – all the people we hire know C/C++ as it is the main development language used in-house. Furthermore, this framework looks extremely powerful as well – able to adapt (live) to a whole range of devices. Installing the Read more
After 16 weeks, 80 days and approximately 640 hours, my time at Aeste Works finally came to an end on 20th December 2013. It feels like such a long time ago that I was fretting about making it on time on my first day. I definitely feel older and wiser about many aspects of engineering, programming and research and design work. This has been the most fruitful four months of work of my life so far. Although I’m sad that Read more
The penultimate week (yes its been 15 weeks already!) at work yielded some fruitful results as the bitstream was able to be read at an optimized speed and some of the older niggling CRC related issues were dealt with. This involved changing the design of how the SD card is used to store the bitstream and in fairness provides a better solution than changing the initialization function to turn the CRC on and off. Fixing the Bitstream reading stack As Read more
Final day, final post, I will explain the things I managed to finalize this week as well as the thing that I couldn’t get to finish. I created a Flippable Master SPI. This master SPI can flip it’s MOSI and MISO pins depending on the value of it’s configuration register. The device has 4 output ports, SCLK, SS, datA and datB. When the configuration register at address zero is NOT SET datA is an input representing MISO and datB is Read more
This week was one where a big setback was experienced in the stack of code for bitstream reading. The stack was then analysed to find the overhead in the code so that the target read times can be achieved. Other than that, some more modifications were made to improve the overall functionality of the program. It was certainly an eventful week. A big Woops! The error in the current code structure was found when the bitstream upload stack was being Read more
The week was spent trying to look for ways to optimize the file upload time to suit the required objective having made some strides on that path during the previous week. Apart from that, a few modifications were made to the MBR editing function. MBR Partition informations It is important to notice that before the SD card is used with the board, it may have already been formatted for use. This means that the SD card may have partitioning informations Read more
Finalizing continues with the SPI. I have previously made a few changes in SPI while integrating it with the system but I hadn’t verified the functionality of SPI after those changes. The most notable change was that one of my if statements was mistakenly inferring a latch. The if statement was missing an else condition. I tested the SPI and it performed as intended on simulation and FPGA. Moreover, I tested the SPI driver. While the FPGA implementation wasn’t very Read more
