Wishbone Bus Interface
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire these instance modules together using the WISHBONE bus interface. The first question came to my mind was “What is the wishbone interface”?. Wishbone is a flexible design methodology used for Read more
