I have finally completed my internship here in AESTE. I have learned so much here, not just about programming but also learning skills, discipline and time management. For my last week I have finish the basic documentation of my code. The project I have been working on for three months is finally documented. Documenting the application: There are many kinds of method to document code on the web, but we need to select the correct method of documenting it. In Read more
In this week , I had to stop working in verilog for a while and get back to do some adjustment and modification to the project web interface. Actually it is really a good thing to break the routine and do something different from time to time :D. If you still do remember, I was handling the code editor part, the editor so far was running on its minimum capability, it can really be enhanced by adding some more features Read more
This was relatively a short week, as today is Thursday and Friday is a public holiday. Moreover, yesterday we left the office at noon to have a farewell dinner for one of the interns and we did not return to the office afterwards. Simply put, the objective this week to enhance the user experience while using the application. There were some obvious changes that need to be done, but some were just features that will make the usage of the Read more
Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun đŸ˜€ . This week my task was completion of the past weeks work. I had to start writing the verilog module definitions for different components and devices. These modules will then Read more
This week I focus my attention on troubleshooting the problem of the application. As I explained in the previous post of the week, there is a few problems in the application and I have found some solution to solve this problems. Decode signal not exposed in Http Client I refereed to the previous project of Dr Shawn and find out that there is a pair of code that can solve this problem. This problem arises when we are trying to Read more
The functionality of the Inkscape extensions was almost finished last week. Most of the work I’ve done this week was optimization and modification to different parts of the application. Some of these changes were made to the Witty application (in C++) and some were made to the extensions (in Python). Import extension The first of these changes was applying the new naming convention for naming the pins of the elements. I explained the naming convention we implemented first in my Read more
Just to do a quick and dirty comparison of several popular ISAs, I compiled a simple C application that calculates primes using the Sieve of Eratosthenes using the following command: gcc -O2 -c -o prime.o prime.c Then, I compared the output binaries just on memory size using the ELF size command. I used the ARM and THUMB outputs as a benchmark for comparison. $ size prime.arm text data bss dec hex filename 244 0 0 244 f4 prime.arm $ size Read more
While work has been under way on our new processor core, which shall remain multi-threaded using interleaved multi-threading in hardware, we have been searching for a free ISA to use as the base instruction set. Our previous microprocessor was based on the Microblaze instruction set (ISA). While there is nothing inherently wrong with this architecture, it seems to have lost some allure and stagnated for a while. So, I was recently reminded of RISC-V, an ISA that was released last year Read more
I continued working on the the Inkscape extensions that I started last week. I worked on improving and modifying some of the functions of the extensions to make the process of creating components graphics easier. But before that, we had to design and establish a naming convention for naming the components and their pins. Previously for our tests we created simple components manually, and thus we chose temporally names. However, now we are automatically generating an entire library, thus we Read more
In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and wiring between them. If you are following my blog entries you will notice that I have encountered some issues with the switch module as we had two routes to take, Read more
