In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and wiring between them. If you are following my blog entries you will notice that I have encountered some issues with the switch module as we had two routes to take, Read more
Last week I spent most of my time studying the application and try to solve the application problem. Let us first go into the problems that I have discover in the application first. revoking the certificate twice This event is highly unlikely to occur, but there is a thin chance of it happening. Previously I used the email address of the user to store their certificate in the approot. In the revoke directory of approot, I have also used the Read more
This week I focused my study on the various file system to find out the limit of number of certificate that this application can hold. So I first started to search the Internet for the NTFS(New Technology File System) which is developed by Microsft. The quality that I am interested to study from this system is the maximum memory that a file can hold, and the maximum number of sub folder that a folder can have. Then I went to Read more
My task currently is to generate the graphics library for the components that we are going to use in our schematic editor. To be more precise, it is not my objective to create all the graphics for more than a thousand components, but rather find a way to automate and simplify this process as mush as possible and thus, it will not necessary be me who is going to generate that actual graphics. The method we started experimenting with is Read more
In this week I had to continue working in creating Verilog top level module . As I mentioned in my last blog entry, the top level module should contain modules such as: processor, switch and several IOs devices. The instantiation of these modules was completed successfully in last weeks. In this week my work was mainly dedicated to the switch module. The switch is a module that is used -as widely known- to select one IO device to be connected Read more
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire these instance modules together using the WISHBONE bus interface. The first question came to my mind was “What is the wishbone interface”?. Wishbone is a flexible design methodology used for Read more
I did not get into OAuth like what I was planning to do last week. Instead I was tweaking the application and the back end of the whole application. I started with the GUI application of the revoke page. Previously, I tried to do some Auto complete function on the search tab to speed up the process of finding a certificate. But the method that I choose to implement this function is wrong. What I did was to first get Read more
The objective this week was to create the parts (components) library for the schematic editor. The way we have been implementing it until now is very primitive where we need to hard code all the components details. Although it worked very well for a few number of components, yet it will be very time consuming to write the code for more than 1000 components manually. Hence this week I was experimenting with Fritzing and Inkscape. Fritzing is open-source Electronic Design Read more
This week the developing of the project headed toward new direction. Previously I was working mainly in the web development and Witty , starting from integrating the Codemirror with witty to extracting the user objects IDs (Check out my previous blog entries for more information ). This week the task was quite different in term of the language used 😀 . My task was simply to create the verilog top level module from the C++ code . The top level Read more
After the previous week has finished, this week we were back working on our first project. My task was to generate a UCF that will contain the wiring information. At the beginning of week, I had no idea what a UCF file is, nor how to generate it. Also, since the UCF will contain the wiring information, I had to modify my implementation of the schematic editor components, since they did not have ports, thus wires cannot be connected to Read more