Engineering Elegance

Next Step on CPU

The C Program Compilation of RISC-V Angel After weeks of debugging the 32-bit RISC-V engine, discussion with my supervisor, and searching over the internet, I finally found out the problem. The problem is with the stack pointer, the RISC-V Angel is not designed in the way of initializing their own stack pointer. Therefore, I have to initialize the stack pointer manually or to create a new crt0.o that initialize the stack pointer to solve the problem. Fortunately, the manual initialization Read more…

By [email protected], ago

Drivers and I/O Addresses

Well this week the progress was relatively slow, and the output could really approach to zero, although the task at first glance seemed quite easy and that it could be done within one day only 😛 . Picking up from where we left off last week, the total project integration continued. In this week my task was divided into three: first I should modify some part of project which related to Xilinx synthesis tool (XST) and the project file that Read more…

By [email protected], ago

Instruction Set Architecture

RISC-V instruction set architecture (ISA) is designed to support computer architecture research and education, and completely free for academia and industry use. By using the reference of RISCV-Angel, which is running with the RV64 (64-bit) architecture. My task is to make sure that the RISCV-Angel is able to run on the RV32 (32-bit) architecture as well. The debugging of the Hello_World program is not going well as I am still getting the “undefined error 0”. Thanks to my supervisor, whom taught me Read more…

By [email protected], ago

Schematics Modifications

Now for real, the circuit is finished, and I have started with assigning and creating the footprints for the components. There are no one major updates this week, but rather a lot of changes and modifications to the schematics. As usual, here is the visual diff for this week. Additions are in cyan, and deletions are in red. Now to the details. Adding SPI flash memory Originally, there was only microSD card connected to both the FPGA and the PIC18 Read more…

By [email protected], ago

Verilog Integration

This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: To begin with, I’ll first talk about the changes I made on my way of creating the Verilog top level module from the C++ code. If you still remember we Read more…

By [email protected], ago

4-Pin ICSP and USB

Good news everyone, the circuit is finished 😀 ! Well, not so fast! Now everything is connected, but there are some last minute modifications to the circuit that were introduced just now. I will work on those first thing next week, and hopefully, I will start with the PCB layout. Here are the updates for the last week. First, here is the visual diff of the root sheet. Edit from last week: Cyan is Additions, and red are Deletions. In-Circuit Read more…

By [email protected], ago

JavaScript and Witty

This week is pretty challenging, I was assigned on task of putting a CPU into web application. The first thing to be done is to analyze the code of the CPU, it was written in pure JavaScript. The Best Way to Learn JavaScript I found out that the previous learning on JavaScript is too shallow, the knowledge of JavaScript learning from website is always not sufficient to be applied in project. However, the  best way to learn would be hands-on Read more…

By [email protected], ago

Data2mem Verification

Progressing from where I stopped last week, this week I had to finish everything up and make sure that everything works as it’s supposed to. Before I go in details and describe what I have done, I have to clear some stuff that were left from last week up regarding the placement of the BRAM. Location of BRAMs: In my blog entry of last week I have declared that I had some concerns regarding the location of BRAM (Refer to Read more…

By [email protected], ago

Minimal Bitstream Size

I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is just a straight-forward 8-bit binary counter. The results are: LX25 Raw/Compressed: 801556/233934 LX16 Raw/Compressed: 464290/134942 LX9 Raw/Compressed: 340697/118773 The sizes stayed the same with and without CRC checking. Looks like the memory storage needed is between 8Mbits (raw) and 1Mbits (compressed).

By Shawn, ago

Hello World

Hello everyone, my name is Ayman and I am doing my Final Year Project under the supervision of Dr. Shawn Tan. In my first blog post I will describe my project, what I have been doing in the past weeks, and what I will do next. The first paragraph is a general description of my FYP, those familiar with the topic can skip it if they want to. My FYP project is based on a project I want to execute Read more…

By aymansahal, ago
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