Pipelined Design for Demosaic Core
This week, I worked on the design of the circuitry for the demosaic IP core. On previous week, my supervisor and I has come to a conclusion of the usage on HQLI algorithm, as it is more hardware friendly and the result is satisfying as well. The design of the demosaic core is separated into two major parts, which is the buffer and the calculator. As supervised by my supervisor previously, so that I would not go into the wrong Read more