This is my fourteen week in AESTE with Schematic done proceeding to PCB design about 50% done. The PCB design is a Four-layer board, signal -ground – power – signal. I am pretty thankful and grateful to be able to do PCB design, the main reason is because to me, I initially reckon PCB design is the easiest job/task, and since during my studies I already done a decent amount of PCB drawing so I was pretty confident I will Read more
In Aeste, we learn something new every day, except for weekends, because we don’t work on weekends :). Dr. Shawn was here for a few days and it was nice to have his guidance and insights on things. The past weeks I have worked on the project, I kept adding in functions, creating widget, in short, expanding ONE big project file. The various storage requests (delete, create, update, etc.) and different WContainerWidgets (board display, project display and info display) were Read more
This week has been a roller-coaster ride for me. There were times when Wt just refused to be a good sport, times when we made great and wonderful progress and also times when I thought Wt wronged me, but turned out I did not understand it enough. As usualy, I have learned a lot new things about Wt, mostly concerning the graphical and user interface. Interactivity While developing a web app., it would be useful for you to know that Read more
Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on implementation of demosaic core on FPGA. 😆 😆 😆 Using Zedboard to Test the Core This is the first time I use an FPGA, and it came across to be the powerful Zedboard. Although I had some hard time learning to use it at first, but later I found Read more
Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 tutorial from the official Zedboard website, and I found that the tutorial is not working fine for me. The annoying error of XPS about the XPSGuiSessionLock, actually put a hold Read more
This is my thirteen week in AESTE. Getting closer and closer to the end of my internship~ This week I continue with drawing Schematic. 😴 💤 💩 😈 👿 👹 👺 💀 👻 👽 🙌 👏 👋 👍 👊 ✊ ✌️ 👌 ✋ 💪 🙏 ☝️ 👆 👇 👈 👉 Nothing much to share about because its just drawing PCB based on past interns’ work and this link. Drawing schematic is really easy and straight forward. I am using KiCAD for Read more
Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path of implementation, many problems occurs and it was really interesting to tackle them. The Edge of Bilinear Interpolation Bilinear interpolation is a simple and easy method to interpolate the Bayer pixel, which uses side (neighbor) pixels to perform the interpolation. Initially, I was planning to build it with a switching in interpolation algorithm Read more
For the whole week, I’ve been continuing work on my task, which is to build some sort of project manager interface. Last week, I built a simple interface without much functions. So, what I did is mostly creating functions and improving the graphical interface. Requests, requests and more requests As I am working with Google Drive to handle project files (store/delete/upload/download/modify), I need to constantly send requests. In default use, my app is given only project folder access, which means Read more
This is my twelve week in AESTE. Continue fixing some minor bugs for my JQuery with Wt and many studying and planning for my PCB design. Getting Started with having SERVER sending request to CLIENT First I change my ‘CUSTOM’ request into ‘HEAD’ request, and have my SERVER (PIC32 in this case) able to send a header to my CLIENT (Wt in this case). The concept is really simple and the method to achieve it is also very easy, however Read more
This is my eleventh in AESTE. Trying to use Witty (Wt) as a CLIENT to send request to my PIC32 wolfSSL server. My time limit is 3days to get this done. ̿̿ ̿̿ ̿̿ ̿̿ ̿’̿’\̵͇̿̿\з=( ͡° ͜ʖ ͡°)=ε/̵͇̿̿/’̿’̿ ̿ ̿̿ ̿̿ ̿̿ Read more