Engineering Elegance

More restructuring and coding smarter

This week, we Aeste interns had much fun where our boss brought us for movie on Wednesday and a farewell lunch for Peter (bye Peter!) on Friday. As for me, this would be the second last blog post. Using Boost::property_tree Back on topic… I mentioned last week that I was using boost::regex to modify(edit values, delete nodes) json files. It was brain-damage inducing and very dumb. Luckily, Dr. Shawn read my blog and told me about this. Turns out that Read more

By [email protected], ago

Clocking FPGA and LAN8720 with PIC32MZ

This is my fifteen week in AESTE finishing up my PCB design project. ..-“””””-.. .’ ___ ‘. / .”\ `\ \ ; /, ( | ; ; /_ ‘._ / ; | |- ‘._`) | ; ‘-;-‘ \ ; ; “””” / MY \\ ; \ ‘2 Cents’ / ‘._A E S T E_.’ “”—–“” I learn a lot this week not just merely about PCB design but also some life principles, because my supervisor is around this whole week Read more

By [email protected], ago

The Final Week in AESTE

This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM to delay the signal, when it is extremely large cycle to be delayed with. My supervisor pointed me out about the problem. RAM is an expensive component to be used. It is always better not to use it if not necessary. The usage of RAM to Read more

By [email protected], ago

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the software implementation of demosaicing for various demosaic algorithm, and tested them in Darktable software. The darktable software is very convenient because it allows to zoom in to pixel and able to view the difference or to debug the algorithm. Initially, I directly ported the C code that had been written to the Read more

By [email protected], ago

PCB design is NOT easy!

This is my fourteen week in AESTE with Schematic done proceeding to PCB design about 50% done. The PCB design is a Four-layer board, signal -ground – power – signal. I am pretty thankful and grateful to be able to do PCB design, the main reason is because to me, I initially reckon PCB design is the easiest job/task, and since during my studies I already done a decent amount of PCB drawing so I was pretty confident I will Read more

By [email protected], ago

Wt: Code restructuring

In Aeste, we learn something new every day, except for weekends, because we don’t work on weekends :). Dr. Shawn was here for a few days and it was nice to have his guidance and insights on things. The past weeks I have worked on the project, I kept adding in functions, creating widget, in short, expanding ONE big project file. The various storage requests (delete, create, update, etc.) and different WContainerWidgets (board display, project display and info display) were Read more

By [email protected], ago

Wt: A Project Manager 2

This week has been a roller-coaster ride for me. There were times when Wt just refused to be a good sport, times when we made great and wonderful progress and also times when I thought Wt wronged me, but turned out I did not understand it enough. As usualy, I have learned a lot new things about Wt, mostly concerning the graphical and user interface. Interactivity While developing a web app., it would be useful for you to know that Read more

By [email protected], ago

Demosaic Core on Zedboard

Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on implementation of demosaic core on FPGA. 😆 😆 😆 Using Zedboard to Test the Core This is the first time I use an FPGA, and it came across to be the powerful Zedboard. Although I had some hard time learning to use it at first, but later I found Read more

By [email protected], ago

Shooting Troubles #3

Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 tutorial from the official Zedboard website, and I found that the tutorial is not working fine for me. The annoying error of XPS about the XPSGuiSessionLock, actually put a hold Read more

By [email protected], ago

PIC32MZ PPS feature

This is my thirteen week in AESTE. Getting closer and closer to the end of my internship~  This week I continue with drawing Schematic. 😴 💤 💩 😈 👿 👹 👺 💀 👻 👽 🙌 👏 👋 👍 👊 ✊ ✌️ 👌 ✋ 💪 🙏 ☝️ 👆 👇 👈 👉 Nothing much to share about because its just drawing PCB based on past interns’ work and this link. Drawing schematic is really easy and straight forward. I am using KiCAD for Read more

By [email protected], ago