Engineering Elegance

Last Few Steps to Complete a PCB board

This week I finish up my schematic for a new board. This new board is similar to the previous PCB board that I design, only that this board uses Spartan6 TQFP packaging.  Most of the component will remain only some minor changes on the capacitor decoupling. To know the required/necessary capacitor for the Spartan6 chip, follow this link in page14 (Spartan-6 FPGA PCB Design and Pin Planning Guide). I also learn how to insert picture (.png) onto the board. The Read more

By [email protected], ago

Extending Wt::Auth

Working on Wt::Auth and Wt::Dbo library for the past few weeks have given me another glimpse into a few of the many functionalities built into Wt. This time it wasn’t as simple as just using the member functions that were provided. The problem with using a library in general is that it won’t fulfill all your requirements. In Wt::Auth::AuthWidget specifically, there is a default login view model which some people would not prefer. So, what’s left to do is to Read more

By [email protected], ago

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, this link also provide further detail on these processes. The implementation process is the one with the UCF file to be incorporated with, where it is a continuation from the Read more

By [email protected], ago

FPGA and PIC comms

This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it. Add a SPI module As I mentioned on my previous post, my task is to assign the SPI module into the FPGA, to form the communication bridge between the FPGA and the PIC. There are many ways to achieve this, and I had made many guesses before the implementation. The simplest and easiest way that I had Read more

By [email protected], ago

Preparing BOM file

This week I finish up my Schematic and preparing the Bill Of Material (BOM) file for my PCB design. I also study some Bluetooth module to be implemented onto my board. The most common bluetooth modules are ‘HC series’ (HC-05 and HC-06), with ’05’ able to be configured as Master or Slave while ’06’ is fixed. After spending some time studying these bluetooth modules, I learnt that there are many unused pins. Generally only 6pins (3.3, GND, TX, RX, KEY, Read more

By [email protected], ago

Revamping the User Registration & Login

Yay, Oauth feature is working! So previously, I complained that the oauth feature in Wt was not working.  It turns out the error was in the redirection endpoint. However, only GoogleService seems to be successful in identifying the user credentials where FacebookService gave a JSON Exception error.  This is probably caused by the change in the HTTP response of Facebook endpoints. My current objective is to get the GoogleService up and running smoothly, together with the Wt::Dbo. The oauth2 example Read more

By [email protected], ago

User Session with Wt::Dbo

Hello everyone, I have agreed to work part-time for Dr. Shawn, together with Alex and Peter. My work will include completing the front end of the previous project which I had contributed on during my last internship.   The first task I will try to accomplish is creating a user session, which will handle the transactions between the user and server. Example of transactions would include registering the user and saving/updating the user projects and boards. For the purpose, Wt::Dbo library would be used Read more

By [email protected], ago

Project Continuation

After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am working remotely, I have to setup my working environment to be exactly the same in the office. I chose to setup a virtual machine for it, for easier setup purpose. The setup of virtual machine does take some time, and surprisingly after all the installations, it could push and pull from the git Read more

By [email protected], ago

Déjà vu

So…….it seems I am back in Aeste 😅😅😅 My task is to continue the part that was done halfway (PCB board). I started the week by first double check my schematic design then match with the PCB design to find any flaw/weird connection. And of course the first week of work (Déjà vu) I was given a piece of one’s mind for connecting several FPGA’s pin to analog side of the board. As a matter of fact FPGA (Spartan 6) Read more

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Something End

This is my last week in AESTE. It all started with Something New and comes to a close with Something End Week1: Something New – Got scolded magnificently by my supervisor Week2: Network Programming – Working hard not to get scold Week3: CORS and HOTP – Still get scold for not doing well Week4: Crypto stuff – I guess I know what I am doing now? Week5: Internal Flash – Ya Ya, Adding more stuff to project again Week6: Wt: Read more

By [email protected], ago