I was stucked with my work when I could not program the board as I wanted. I made a program of LED blinking and LED being turned on and off using switches. After I synthesized and generate the programming bit file, I used iMPACT to load it to the board but I keep getting “Program Failed”. I checked my codes and started to think that the software or the board is not working as it should. After I tried to Read more
This week I spent most of my time testing the networking section of the board. Firstly I tried to run a simple TCP server code on the board to confirm that it is working. unfortunately, I could not get any result from the board. That called for serious debugging and problem-solving. I then tried to check the input voltages on the ethernet chip, just to make sure, the chip is connected to power. The test suggests there are no power Read more
Day 1 & 2: Upon my arrival, I was warmly welcomed and informed that Dr. Shawn wasn’t in office today. As a matter of fact, the other interns mentioned to me that the number of days per week that Dr. Shawn is available in the office was based on RNG. One intern in particular (Sina), was working on an in-house designed and programmed board with a PIC MCU and a Spartan FPGA chips. Sina gave me a brief briefing on work and the project. Read more
This week had been exciting for me as now I have the Digilent Atlys Spartan 6 board to play with. Dr. Shawn taught me on USB over IP, to have the board connected to the server. Before doing anything, Dr. Shawn instructed me to go through the reference manual of the board first, this is very important as the connection of the jumpers should be checked before the board gets turned on. Besides the board, now I also have the Read more
This week the board finally arrived and immediately I noticed that the ethernet jack was missing after notifying Dr. Shawn I then started testing the board with an led blink test program and verified the PIC and LEDs are working. I then moved to testing the USB with a simple comport test code to send a string and verified that the USB is connected and working properly. Next step was to test the FPGA, so firstly I tried to put Read more
This week I started with having both SPI master and SPI slave verified for its functionality. Besides checking for the results of waveform graph manually, I also made sure it passed the automated test bench. This applies for all four modes of SPI which differs from the aspect of clock polarity and clock phase. I was glad I finally could get it done as I had problems of simulating the output at first. I proceeded to the UART but again, Read more
This week I managed to finish the basic version of the code. It now establishes a network and then uses CORS protocol to communicate with the client. The client will then be able to erase the FPGA or flash and write a new set of data by entering the correct sequence of commands under CORS protocol. In order to increase security, an HOTP is also required to perform some of these operations. This HOTP is generated from a random number, Read more
I was not capable of verifying the codes that I modified because I had problems understanding how the output signal waveform should and should not be. I was frustrated with myself that I could not even understand the simple communication protocol, GPIO. Dr. Shawn was also angry and had to explain how it works in which the Wishbone bus and the GPIO signal must be observed to confirm whether or not the output works according to its inputs. Dr. Shawn Read more
This week I worked on flash programming. Previously I managed to use flash driver to accomplish erase and write operations. However, the library does not include a read functionality. The code was still using NVM library to perform a read operation. I came up with a function to perform a flash read without the NVM library. It basically reads the physical address on the memory and saves it to a variable. The code can now receive data over an HTTPS Read more
Test bench can be deterministic or self-checking. In deterministic test bench, the design’s output are simulated according to the design’s state and inputs specified in the test bench. A designer would then have to validate that the outputs are working as it should. Meanwhile, in self-checking test bench, expected results are generated thus allowing the simulator to verify whether the actual outputs are tally to the expected outputs. This means that the designer does not have to go through the Read more