Engineering Elegance

LLVM: Customize your Instructions.

For the past few weeks, I was given a task by my supervisor. The task sound simple, whenever there NOP (No operation) instruction will be use, LLVM should change it into XOR R0, R0, R0 which basically doing nothing since in aeMB, register zero (R0) always have zero values. NOP –change to–> XOR R0, R0, R0 So I start digging. First I look into *InstrInfo.td because thats where all target specific instructions were define. And the tablegen will automatically generate Read more

By tedxmmu, ago

uCLinux: Tick Rate

With a large number of kernel functions are time-driven, the time management in kernel is very important. The frequency of the system timer (tick rate) is programmed on system boot based on a static preprocessor define, HZ. The value of HZ is architecture-dependent, and it is defined in: <asm/param.h>. The tick rate has a frequency of HZ hertz and a period of 1/HZ seconds. For example, by default the architecture defines HZ to be 100. Therefore, the timer interrupt on the system has a Read more

By cyberglory, ago

After life: There is a Need to Improve

I had officially completed my internship life in AESTE. Finishing my internship makes me wonders about my future. This feeling was never so intense. I never worried about my future so much before, when I was in my university. My supervisor told me that engineering is all about efficiency. He showed how naively I had implemented my code, without considering much about readability and capable for other people to handle in the future. These are really inspiring. These does not Read more

By tanagabiru, ago

Internships at AESTE

Listen to one of the interns here talk a little about his internship experience at AESTE. The work we do is HARD – but fruitful. The working culture here is different – in a good way. You get to meet other interesting people – who will enrich you. An internship at AESTE is guaranteed to push you to discover strange new things about yourself. Read what other interns learned through their experiences here. Apply now!

By Shawn, ago

Z: Doesn’t She Look Good

Anyone who has a hobby would understand the satisfaction of completing something on which he or she enjoyed working. It doesn’t always look marketable, it doesn’t always look fashionable, it doesn’t always look picture-worthy. But it always looks good to the creator. Anyone who has a job would understand that that is never enough. Anything that looks good only to its creator has little value to the rest of the world and is largely irrelevant in the grand scheme of Read more

By philipzloh, ago

Misunderstood Motivations

In the latest blog entry from one of our AESTE interns, he raised a couple of pertinent questions with regards to the very raison d’etre at AESTE. I thought that this might be an opportune time to address the issue. First, I shall address a very commonly held misconception – “What use is the fastest multi-threaded 32-bits when others have already multi-core 64-bits”. Global Microprocessor Market Most people will probably think along the same lines except people who are in Read more

By Shawn, ago

Code is never finished.

Towards the second half of my internship, I extended my working hours. I knew that if I don’t, I’ll never be able to achieve anything in the end. Now the day had come that I have officially finished my internship. My code still have a lot of bugs and holes. My triumph had failed me. AESTE is at the level that will not be fully understood by anyone. Many of my course-mates are skeptical on the future of AESTE. Before Read more

By tanagabiru, ago

ASH1: Architecture

After summarizing USB Operations, time to kick off the ball for the match of ASH vs. IOP The general view of ASH1 processor is as the following: ASH1 is a stack-based processor, where the majoroty of the operations will be done on a stack, this participates in reducing the instructions operands. The initial plan was to make ASH1 a multi-cycle processor but with the introduction of an instruction memory unit, ASH1 is generally a single-cycle processor with the exception for Read more

By mesopotamiascorpio, ago

ASH1: I/O Operations

Hi again. It’s been a long time since my last blog. So, let’s catch up with ASH1 updates, The plan now is to take into consideration USB operation first with the intention to include all other I/O operations afterwards (especially MAC Ethernet).. In order to get familiar with USB operations (Rev1.1), I had to go through several references, among them are: USB COMPLETE ( a book) by Jan Alexon. USB Specification USB Made Simple USB in a NutShell In general, Read more

By mesopotamiascorpio, ago

LLVM Scheduling

LLVM is a compiler project which start as a research at University of Illinois and now has grow to become a massive project and involve in both commercial and open source, as well as research. LLVM is licensed under “UIUC” BSD-Style license. Recently, the latest Apples also start using LLVM in their recent release Xcode 4. LLVM is said to be twice faster than gcc, easy to expand, easy to optimize, and and designed for today’s modern chip architectures. Hence, Read more

By tedxmmu, ago