Chronicles from our peeps.
This is going to be my first weekly blog post at Aeste! I just joined this company as intern. As for the first week of my internship, Shawn asked me to study Git and do some C programming tutorials just to make sure that my understanding of the C language Read more…
So it has been 2 weeks since the last time I’ve blogged and a lot have happened since then. Today we just finished the design and testing of the SPI peripheral device. That includes an SPI Master and slave that are wishbone compatible and a dummy master to test those Read more…
On my fifth week here, I finished up the SPI that was compatible with the Wishbone bus. I was able to have it working for the four modes of the SCLK. I had to make many changes to the design because I did not have the right idea of the Read more…
My first week at AESTE, I was introduced to something that I have never used before which was the new operating system of Ubuntu. Being a complete tyro at it, I was a little puzzled at how this operating system works. I was required to learn about the GIT software Read more…
This lab was really annoying in terms of things that didn’t want to work When trying to export hardware for SDK in PlanAhead error shows [Common 17-49] Internal Data Exception: xps application failed SDK requires gmake, we can solve it by simple linking: cd /usr/bin sudo ln -s make gmake Read more…
As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I Read more…
After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal Read more…
In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. Read more…
Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange Read more…
This week wasn’t the brightest. Our tasks from last week has been dragged to this one which is designing a GPIO and a wishbone interface and a dummy master to drive the GPIO, the later being my task. It was a cloudy day full of rain and sweat, definitely not Read more…