Chronicles from our peeps.
Here come the final week of my internship. After I have done my code checking and debugging for Load and Store instruction implemented earlier, I started to work on my main task of the week that is to implement IMM instruction in pipelining. This task actually wasn’t heavy but was a Read more…
Work on designing the PCB layout continues in earnest. We encounter a few software issues relating to the hardware of the task, which prompt some worried thoughts. As always, here’s a look back at the previous week. Click here to skip to the conclusion. Pin Assignments During design it became Read more…
This week we have managed to get an SOC that connects AEMB to SHA1 accelerator and a GPIO. Having only one device at each bus of the AEMB doesn’t require much effort in terms of SOC. The software that we used for testing contained our driver for SHA1. Our demo Read more…
It turns out that issue of connection timeout, random protocol data is caused by the fact I did not call the write function after TCP and Ethernet layer processes. The write function is then called in the Ethernet layer (ETH97J60.c). The function that is modified is MACGetArray(). After this modification, Read more…
This week was really a busy week and it passed so fast that I didn’t even realize that today is Friday again! I have spent a lot of my time fixing the bugs in the SHA1 driver when it was tested on the Simulator. Later, I started to test the Read more…
This week although wasn’t that productive but I still manage to start working a little on the following new stages that are the 4th stage-Memory Access and the final stage-WriteBack. The first 2 day of the week I continue on code checking before further implement the following stages. Carry bit Read more…
During my 10th week at Aeste, I continued my unfinished business from the 9th week: bit banging the gpio to implement a custom 8 bits wide bus. I spent most of my time this week debugging the gpio driver for the custom bus. My code was ready at the beginning Read more…
My last week surprisingly didn’t involve any more hardware and I had opportunity to play again with some good old C. The task for this week was to write the missing software part for the ECDSA, that is the whole algorithm for signature generation and verification (keeping in mind that Read more…
With the footprints done, wrestling with PCB design continues as usual with component placement and routing. Also this week, I hit a minor snag with regards to simple yet confusing aspect of my task. Blow-by-blow account below, but click here to leap to the summary. Layout & Design Rules As Read more…
I’ve managed to completely remove the Icache from AEMB. Simulation and FPGA implementation were both a success. However, after the edits AEMB now runs slower because it has to fetch each and every one of it’s instructions through at least two Wishbone cycles. It’s worth mentioning that Before removing the Read more…