Chronicles from our peeps.
The penultimate week (yes its been 15 weeks already!) at work yielded some fruitful results as the bitstream was able to be read at an optimized speed and some of the older niggling CRC related issues were dealt with. This involved changing the design of how the SD card is Read more…
Final day, final post, I will explain the things I managed to finalize this week as well as the thing that I couldn’t get to finish. I created a Flippable Master SPI. This master SPI can flip it’s MOSI and MISO pins depending on the value of it’s configuration register. Read more…
This week was one where a big setback was experienced in the stack of code for bitstream reading. The stack was then analysed to find the overhead in the code so that the target read times can be achieved. Other than that, some more modifications were made to improve the Read more…
The week was spent trying to look for ways to optimize the file upload time to suit the required objective having made some strides on that path during the previous week. Apart from that, a few modifications were made to the MBR editing function. MBR Partition informations It is important Read more…
Finalizing continues with the SPI. I have previously made a few changes in SPI while integrating it with the system but I hadn’t verified the functionality of SPI after those changes. The most notable change was that one of my if statements was mistakenly inferring a latch. The if statement Read more…
The week was spent in continuing the ground work done on the Synchronous USART to optimize the Reading process which will subsequently program the FPGA. After solving the problem faced in the week before, time was spent in trying to get the SD card to read the bitstream data as Read more…
This week and the coming one will all be about finalizing, testing and documenting everything. This needs to be done for all t3pi I/O devices. In addition, there is a few bugs in c3rdas accelerators that need to be solved. Currently I’m writing my technical report about my internship. I Read more…
The project becomes closer to completion with the top level creator being as done as possible. In this post I’ll start by explaining the top level creator and it’s awkward status of being “as done as possible”. Next, I’ll try to make the big picture of our project clearer by Read more…
The optimization of the firmware continued with the focus being on the SD card reading stack. A look into the USART’s synchronous mode functionality was also taken to try and understand how that works. There was also a lot of time spent trying to set up scenarios to break the Read more…
Following the completion of the Ping-Pong Upload mechanism, its time to step forward to system optimization for the PIC firmware. This includes many separate portions looked into during the week to try to enhance the system performance and deliverable. The tasks include: i)optimization of the read/write functions ii) clearing up Read more…