Chronicles from our peeps.
Great! My blog is in its third decade now. Happily declaring that the project is getting close to the end. This week the final main functionality has been added to it. The project now has the ability to compile the user C++ code, synthesize the top module and finally Read more…
This week’s post is relatively short, as I spent most of the time doing the actual routing, so nothing much to talk about here! However, I will highlight some of the concepts and considerations that are important while routing. First let me say that all the board connections have been Read more…
Debugger After trying on the break point implementation last week, I decided to work on interface with Sumia and Islam’s code. As pre-discussed with my supervisor, the simulator should be the back-end engine and should not have any visible interface in the Web Application. In order to ensure things going Read more…
Sadly I’ve just realized that my internship is getting closer to the end. Cannot really describe how I feel… Just mixed feelings. But what I really know is that this period has really enriched my life in all aspects. lol, Stop being so dramatic and get back to the work Read more…
Last week after finishing the schematics I started with assigning and creating the components footprints. This was the first thing I finished this week, though it took some time to finish them. Afterwards, I started with placing the components on the board. Placing Components First things first; our board is Read more…
The C Program Compilation of RISC-V Angel After weeks of debugging the 32-bit RISC-V engine, discussion with my supervisor, and searching over the internet, I finally found out the problem. The problem is with the stack pointer, the RISC-V Angel is not designed in the way of initializing their own Read more…
Well this week the progress was relatively slow, and the output could really approach to zero, although the task at first glance seemed quite easy and that it could be done within one day only 😛 . Picking up from where we left off last week, the total project integration Read more…
RISC-V instruction set architecture (ISA) is designed to support computer architecture research and education, and completely free for academia and industry use. By using the reference of RISCV-Angel, which is running with the RV64 (64-bit) architecture. My task is to make sure that the RISCV-Angel is able to run on the Read more…
Now for real, the circuit is finished, and I have started with assigning and creating the footprints for the components. There are no one major updates this week, but rather a lot of changes and modifications to the schematics. As usual, here is the visual diff for this week. Additions Read more…
This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: Read more…