Chronicles from our peeps.
Time passes quickly and my internship has come to an end. Throughout this journey I have learnt a lot and gained a lot of new insights especially from my supervisor, Dr Shawn. I would like to extend my appreciation to Dr Shawn for all his guidance and advice in this journey. Read more
Now that my week 3 has passed, I would say I am not as clueless as before. I have shown my previous week’s work on witty application with backend WResource to Dr Shawn. Subsequently it was followed by a session defining my aims in the project I have been assigned. Read more
This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that Read more
First day of work already got scolded by the Boss, “Another two useless Intern!”, “Call Rodney now,” “I’m thinking whether to fired you 2 now, cause i won’t lose anything”, “simple things also cannot do”, “if you don’t understand read more lah, I give you all so much time and Read more
Another week has passed in AESTE and although Dr Shawn was not around for the time but there was no lacking in my learning curve. My senior interns (Sumia, KY and Islam) had always tried to pass down the knowledge they have earned throughout. I am more than blessed to Read more
FreeRTOS capable to run multiple tasks by using tasks switching method. Scheduler is the kernel who doing the task switching operation. The scheduler will changing the task into running state when it is require. But when the yield, block or suspend functions is called, the scheduler will switching other task Read more
This week my task focus is to survey about the price of electronic components for a project. This is my first time doing such a survey for a real industrial project. I get to see how a Bill of Material (BOM) is listed. The first thing I learnt is the Read more
This week I continue the work on the SSL. After I included all the necessary files, it return errors of ‘TCB_uRam’ cannot fit the section. At first I thought it was running out of RAM space like another case that I experience before. Since the SSL is a very large Read more
I am officially in the midst of my internship now, and decided to try something new to me, which is chip design. I was given the tools of Atyls Spartan 6 FPGA development board for the development of chip design. The Xilinx ISE tool There are many documentations provided by Read more
This week I was given another task about the CCD optical sensors. CCD is called Charge-coupled device where it is capable of transforming light pattern from an image into an electric charge pattern just like an electronic image. It can collect, store and transport electrical charge from one element to another. Each pixels Read more