Chronicles from our peeps.
I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more
Hello everyone, and happy 2019. I’m back writing the first blog for the new year and to inform my dear readers, whoever it may be, of the status of my project. Hoping back into the project, the only problem that I have to deal with now is getting the automatic Read more
I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more
I’ve finally implemented the base functionalities of the project, and tested that everything works as expected. The only thing that I have left hanging in the dark is finding out how to get the automatic installation of client certificates into browser working. Nevertheless, the application is almost ready to be Read more
This is my fourth week as an Intern at Aeste Works. My main target this week was to configure the PIC32MX microcontroller as a Universal Serial Bus Communications Class Device that utilizes the Ethernet Networking Control Model (ECM) in allowing the exchange of Ethernet-framed data between device and host. The first Read more
Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important Read more
This week is the week where I try to finish up all of the basic functionalities of the application. What I had left was to figure out how to create a custom x509v3 extension with Botan C++. As recommended by Dr Shawn, I used the UserRole extension, as shown here. Read more
This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan Read more
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more
