Chronicles from our peeps.
This is my fourth week as an Intern at Aeste Works. My main target this week was to configure the PIC32MX microcontroller as a Universal Serial Bus Communications Class Device that utilizes the Ethernet Networking Control Model (ECM) in allowing the exchange of Ethernet-framed data between device and host. The first Read more
Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important Read more
This week is the week where I try to finish up all of the basic functionalities of the application. What I had left was to figure out how to create a custom x509v3 extension with Botan C++. As recommended by Dr Shawn, I used the UserRole extension, as shown here. Read more
This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan Read more
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more
The major thing that I managed to get done by this week was the implementation of interfacing with the WooCommerce REST API. As a reminder, this is only done by the application when a new subscription for an organization certificate is made, and the customer also chooses the option to Read more
In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had Read more
This week was all about catching up. The project that I will be working was introduced this week by Dr Shawn which looked both interesting and challenging at the same time. I was assigned to upgrade and improve the functionality of two main parts in an existing design software. As Read more
This week, I made one more step of progress by implementing the Certificate Revocation List (CRL). The CRL holds a list of certificates that had to be revoked before their expiry date for a particular reason. In our case, that reason would be to handle the case where the customers Read more