This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: Read more…
Progressing from where I stopped last week, this week I had to finish everything up and make sure that everything works as it’s supposed to. Before I go in details and describe what I have done, I have to clear some stuff that were left from last week up regarding Read more…
This week I have started working on initializing the block ram (BRAM) with some content. There are so many ways to initialize your memory with. You can for example directly initialize it form your HDL code. But this way is inefficient and tiresome as you have to keep changing your Read more…
In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools and concepts. In next paragraphs I’ll try to summarize what I have learned so far .. So let us get started ! Read more…
By approaching this week we can finally say that we have completed the first half of the internship successfully . According to our university internship program , the second half is dedicated for the student to carry out a specific project that is related to the host company, so here Read more…
In this week , I had to stop working in verilog for a while and get back to do some adjustment and modification to the project web interface. Actually it is really a good thing to break the routine and do something different from time to time :D. If you Read more…
Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun 😀 Read more…
In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and Read more…
In this week I had to continue working in creating Verilog top level module . As I mentioned in my last blog entry, the top level module should contain modules such as: processor, switch and several IOs devices. The instantiation of these modules was completed successfully in last weeks. In Read more…
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire Read more…