During the last week, I worked on developing an assembler for ASH1! I have always wondered about the assemblers & compilers design… with AESTE, I had the chance to explore this field. ASH1 assembler is developed using MATLAB. It takes an assembly language source file (text file) and translates it Read more…
After integrating Ethernet operations into ASH1.. I though of demonstrating ASH1 as an IOP .. so I looked for a simple I/O operation, yet a simple one to make my life easy when I am writing the code for it in binary. I decided to make ASH1 works as an Read more…
Cyclic Redundancy Checksums generation and checking were among the challenging things in implementing ASH1. Looking for the accurate way to calculate/check CRCs took me a lot of time as it was confusing in terms of the following: Bit Orientations (LSB first or MSB first). The Initial Value of the CRC Read more…
Back-off is an important feature of the Ethernet MAC protocol. After a collision is detected through the MII/RMII interface, ASH1 should stop transmitting (there are more specific details about when exactly to stop transmission) and then reschedule its retransmission by generating a period of time to wait before retransmission. The Read more…
I have mentioned many times that ASH1 should be as small and as fast as possible… The current version of ASH1 is able to perform USB functions pretty good ( more specifically 1.5 Mbps USB operations) and other simple I/O operations. However, getting myself into Ethernet and trying to integrate Read more…
As ASH1 is an IOP, it should be able to perform Ethernet operations. In the past days, I have been going through Ethernet references and literature, I must say it’s much more fun than USB. “The diagram … was drawn by Dr. Robert M. Metcalfe in 1976 to present Ethernet Read more…
ASH1 has 2 output ports and 1 input port whose specifications are like the following: Input Port 0 (iport0) An 8-bit input port with 4 schemes of encoding (table 1): Encoding Scheme Description 00 Non-Return-to-Zero-Level (NRZL) 01 Non-Return-to-Zero-Inverted (NRZI) 10 Differential Encoding with Non-Return-to-Zero-Inverted (NRZI) 11 (same as 00) – Read more…
ASH1 is growing and the design is being modified continuously to allow for further flexibility and capability in performing I/O operations. However, these modifications won’t be drastic. ASH1 core is there ! So in the future, there will be slight changes in the instruction set or components. The design flow Read more…
ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing with Signal Width Direction/ Type (with respect to ASH1) Master CPU clk 1 i reset 1 Read more…
As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features. Below is the block diagram of ASH1. It consists of a data stack, a control unit, a program counter, an arithmetic/ logic unit (ALU), a cyclic redundancy checksum (CRC) Read more…