Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important Read more…
This week I have started working on initializing the block ram (BRAM) with some content. There are so many ways to initialize your memory with. You can for example directly initialize it form your HDL code. But this way is inefficient and tiresome as you have to keep changing your Read more…
In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools and concepts. In next paragraphs I’ll try to summarize what I have learned so far .. So let us get started ! Read more…