This week I spent most of my time testing the networking section of the board. Firstly I tried to run a simple TCP server code on the board to confirm that it is working. unfortunately, I could not get any result from the board. That called for serious debugging and problem-solving. I then tried to check the input voltages on the ethernet chip, just to make sure, the chip is connected to power. The test suggests there are no power problems. I also verified that there is a clock signal going to the chip. After consulting with Dr. Shawn, he told me to start from the basic and make my way up.

I verified that the MAC can be established and run without any problems. Since MAC is running, then I tried to utilize the loopback functionality of the device to verify that the chip itself is working. Loopback can be enabled from Harmony Configurator in MPLAB. The second test I performed was to physically connect the Tx and Rx wires in a network cable together so that the board will receive whatever it transmits. This test verified that the TCPIP is also successfully initialized. Therefore, packets can be sent and received. I also tried to ping the board itself, by setting a fix IP address on the board. It resulted in link activities which means the board is transmitting something.

At the moment if the board is connected to the network at 100 Mbps, the board will continuously restart. However, if it is connected at 10 Mbps then MAC and TCPIP will both be established. Although TCPIP is working, the board is still unable to get an IP address when it gets connected to the network. This means that it can not be pinged from the server either. At this stage I figured that it is very possibly a clocking issue, so Osama (the new intern) and I tried to recreate the same problem on the old board. After tweaking the clock we managed to get the exact same result with the old board. This means that even a minor change in the clock signal can totally change the behavior of the board.

In the old board, REFCLK is used to supply the clock signal to the ethernet chip. However, in the new board, the clock signal is connected to CLK0 (OSC2) which is equal to PBCLK1 divided by 2 (CLK0 = PBCLK1 / 2). Unfortunately, so far our founding suggests that PBCLK output is not accurate enough to meet the 50 ppm requirement by the ethernet chip (LAN8720).

Farewell

This Thursday we had a small farewell/welcome lunch and movie, which was really good. It was a great afternoon with Dr. Shawn and my colleagues.