Week1: Spartan-6 Configuration Interfaces

Another week, another intern. I started on 28 June and was told by my supervisor that I’ll be working mainly with Jia Xien in contributing to the hardware and firmware aspects of Aeste’s current project. After going through the basic tutorials on Git and C, I dove right into my task of the week: researching and weighing configuration interfaces for an FPGA. If you’re feeling an onset of TL;DR-itis, feel free to skip to the last paragraph.

Problem statement

When the Xilinx Spartan-6 FPGA is first turned on, it is in a “blank” state and a bitstream file containing configuration data has to be fed into it. As such, the FPGA is usually connected to a boot PROM or a microprocessor that automatically begins the .bit file transfer when the device starts up. For this project, the 2.7 Mbit configuration file will normally reside in an attached microSD card and will be passed to the FPGA via a microcontroller during the configuration sequence. After this initial process, the FPGA will become the master of the PIC, controlling it and accessing its functions.

There are various methods of setting up this configuration interface as outlined in the User Guide [1]. Broadly speaking, they can be classified as parallel or serial connections, and whether the Spartan-6 is acting as master or slave.

A number of considerations include:

1. Pins required – A greater number of pins will further complicate the PCB routing.
2. Post-configuration – Can the pins used for configuration be re-purposed as general I/O pins during nominal operation?
3. Speed – Can the .bit file be transferred in an acceptable time? Is the limiting factor the FPGA or in the PIC microcontroller/ microSD card?

The selected PIC can at most generate clock cycles at 41.67MHz [2], and that is with the benefit of external oscillators as well. Meanwhile the microSD card read speed is hugely variable depending on the card class, manufacturer and firmware, so for the current Class 4 test cards in use for testing, we estimate it to be ~30 Mbps. Expect this value to change as we do further testing.

JTAG

First off, there is the JTAG configuration method that is common across industry (IEEE Std 1149.1 ). This FPGA has a dedicated four-wire port that is always available for configuration regardless of the mode pin settings. However, the main use of JTAG is to be a standardized debug & config connection. Normally, the FPGA is attached to a JTAG signal header, which can be driven from a processor or a programming cable. As such, it was decided to rule out using this as the primary configuration option.

Slave Serial Mode

Does exactly what it says on the tin. This is a synchronous serial mode in which the FPGA receives one bit per clock cycle from the PIC. From [3], only 7 pins are required for this mode. Besides a few dedicated config pins, these pins may be reused to control the PIC after FPGA configuration.

The maximum FPGA clock speed for this mode is 80 MHz, which means that the theoretical .bit file transfer time should be 34 ms. However, this transfer process is limited by the PIC and the microSD card, hence the maximum possible clock speed is 30MHz which gives a minimum loading time of 90 ms.

SelectMAP

This Xilinx’s proprietary 8-bit (or up to 16-bit) bidirectional data bus interface to the slave FPGA that can be used for both configuration and readback. The number of pins required is much higher at 17 pins, but once again most pins can be re-utilized for other functions.

Recommended by the manufacturer when speed is a priority [3], the expected SelectMAP data transfer rate is eight times the rated clock speed of 50MHz, giving a time of 6.9 ms. Of course, the microSD card becomes the limiting factor again, so the transfer time goes up to 13.7 ms.

Serial Peripheral Interface (SPI)

SPI is another industry standard and is implemented in the FPGA very similarly to the aforementioned Slave Serial Mode, except with the Spartan-6 acting as the master during configuration. For this reason, the manufacturer suggests in [1] that it be used in conjunction with a flash PROM. However, the PIC for this project itself has been designed with an SPI bus [2], has dedicated SPI control & status registers and can be enabled to operate in slave mode. So this should be a viable configuration option although prior examples in user guides & application notes are scarce.

The FPGA is capable of x2 and x4 data input modes as well, but the normal x1 mode would suffice here. The total number of pins then required is 10, and again most pins can be re-purposed afterwards.

The maximum FPGA clock speed is 40 MHz with a load time of 67.5 ms, but this becomes 90 ms once more due to the microSD card.

Byte-Wide Peripheral Interface (BPI)

This mode is unsupported by the PIC, so it was decided not to pursue this line of investigation.

References

[1] Spartan-6 FPGA Configuration User Guide, UG380 (v2.3), 6 Jul 2011, Xilinx.

[2] ‎PIC18F97J60 Family Data Sheet, 2011 , Microchip Technology.

[3] M. Peattie, 24 Aug 2009, “Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode ”, XAPP502, Xilinx.

So, the candidates for potential FPGA configuration interface have been reduced to SelectMAP (slave parallel), Slave Serial Mode and Master SPI. Which config will reign supreme? That is up to you, dear reader, to find out next week!