This week, I finished connecting each module to CPU via a customizable switch. I learned the importance of flexibility in design while I was designing the naming convention for different modules and their signal’s name. Other than creating a working design, I make sure the design is elegant and simple. Also, I recorded the technique I used in Wiki on Github to ensure the next intern will understand it clearly.
Next, I will be working on generating a UCF file. I need to make sure the naming convention is constant throughout the while project to prevent conflicts between Verilog side and JSON side. There are many ways to accomplish this task because I can either modify the Verilog side or json side. Thus, I will consider every possible way and deduce a best one to minimize tradeoff for the design and yet create an elegant technique.
Connection between fpga and i/o devices is stated in Json file. I will have to make sure every single device has its own unique name and so does the pin. If I get to finish everything quick enough, I will spend the rest of my internship inventing a customizable switch which is a task I very much look forward to. But before that, I will make sure I set my priority right. I will focus on generating UCF file and inventing naming convention for i/o devices and their pins.
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