Clocking FPGA and LAN8720 with PIC32MZ

This is my fifteen week in AESTE finishing up my PCB design project.

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I learn a lot this week not just merely about PCB design but also some life principles, because my supervisor is around this whole week to teach/guide us. For my PCB project I did not make any changes to my components but some minor pins remapping. I also restudied some PCB designs from the net regarding LAN8720 PCB layout, Clocking FPGA, Clocking LAN8720.

My 2Cents about LAN8720

• Its a really cheap PHY chip.
• Could be configured to run MII or RMII mode
• The Schematic design must be referred to this Schematic_Checklist
• The PCB design layout must be referred to this Routing_Checklist

My 2Cents about Clocking FPGA

• PIC32MZ will be providing a clock signal for FPGA device
• There are many ways to work this around: OSC2 pin, SCK pin (SPI peripheral), SDA pin (I2C peripheral), REFCLKOx pin (PBCLK peripheral)
• The easiest method will definitely be using OSC2 pin, because this pin will output half of PBCLK1 clock signal. eg: if PBCLK1 = 100MHz, then OSC2 = 50MHz (Keeping in mind all PBCLKx peripherals have a maximum clock speed of 100MHz with SYSCLK running at max speed – 200MHz!)

My 2Cents about Clocking LAN8720

• For PIC32MZ there are several ethernet interfaces available to run an ethernet PHY (RMII, MII)
• I will be using RMII configuration. (uses less pin)
• The tricky part for this mode is the clocking to an external PHY chip. Because PIC32MZ will not provide the clock to PHY chip from ethernet pins.
• The workaround for this problem is either for LAN8720 being drive by an external clock (50MHz crystal oscillator) or PIC32MZ provide the clock signal from other PBCLK peripherals (REFCLKO, SPI, OC – Output Compare by providing a PWM signal)
• A good starting point will be to study ‘Ethernet Controller‘ reference manual
• And ‘EREFCLK’ pin for PIC32MZ must be connected to the clock signal provided by PIC32MZ peripheral pins and LAN8720 ‘CLKIN’ pin

My 2Cents about my supervisor – Dr. Shawn

• I’ll leave it for my next and final blog~ ﴾͡๏̯͡๏﴿ O’RLY?