While entering the last stages of creating the PCB, there are still some changes to be made to the circuit. In addition to these modifications, this week the solder mask, solder paste, and silkscreen have been created. Also, finally I was able to come up with an estimate for the power consumption of the Spartan-6 FPGA. Here’s what you need to know.
Schematic and layout modifications
Although the board has been laid out and successfully routed, some changes to the schematic are still being made. That’s not a problem as this is expected when designing a board. These modifications will of course result in some changes to the layout.
Adding 2 rows to the digital port
The Arduino Rev 3 has additional 2 pins in its digital port. These pins are connected to the I2C pins of the microcontroller. Since our board should match the Arduino footprint, we added these extra pins. However, they are connected to the FPGA not the PIC18. This will allow more flexibility in terms of what these pins can be used for.
The addition of these rows of pins decreased the space between the pin array and the Ethernet jack. Therefore, the jack was moved, which leads me to the next point.
Adjusting components positions
The Ethernet jack needed to be moved out of the way of the new two rows of pins. Also,
I was asked by my supervisor to move the jack as well as the USB port inside the board so they are not protruding outside. The regulators were also moved to match their center with the FPGA center. Well, that’s just an eye candy and doesn’t affect their functionality. Lastly, the memory card socket and the JTAG header were slightly moved as well. These adjustments, however, did not change the routing of signals much.
Estimating the FPGA power consumption
Power consumption should have been done in an early stage of the board design. However there was a problem with downloading Xilinx power estimator XPE. Finally I was able to get it and use it to estimate the FPGA power consumption. Generally, the spartan 6 family FPGAs don’t have high power consumption, especially for LX9 since it is one of the low end FPGAs. The XPE confirmed this prediction. Here are screenshots of the spreadsheet.
Xiinx in XPE user guide recommended against exaggerating the system requirements and designing “to be on the safe side” as such exaggeration will results in an unrealistic high estimates. Even though, with such high assumptions and utilization percentage of more that 90% of the FPGA resources, its consumption did not exceed 300mA. A note to keep in mind is that I/O consumption is not included in this estimates as it depends on what the user is connecting.
The board is designed to provide up to 1.5A. Based on these values, and the PIC18 power consumption, it is safe to assume that providing enough power for the board will not be an issue.
Solder mask, solder paste and silkscreen
The technical layers on top of the copper layer include solder mask, solder paste and silkscreen. For the first two, KiCAD is very helpful as it automatically generates them based on the pads on the board. The designer only needs to specify the clearance required and minimum width for the solder mask. Once again we were restricted by the manufacturer rules for the solder mask minimum pads. The recommended solder mask pads opening by Xilinx is 0.5mm, where as the smallest pad allowed by the manufacturer is 24mil → 0.6mm.
Finally, the last technical layer needed for manufacturing is the silkscreen. Most of the library components already have their outline in the silkscreen, as well as their references. All I needed to do for them is to reposition them. Other than the components references and outlines, I added many other info on the silkscreen, such as the ports pins names, logos, and website. The info on the silkscreen might change a bit, and more info might be added, but for now, the silkscreen looks good enough.
That’s it for now. Talk to you next time.
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